| commit | 50b0ea0cf5cf4a8516da661947bbc69881c02039 | [log] [tgz] |
|---|---|---|
| author | R. Timothy Edwards <tim@opencircuitdesign.com> | Mon Nov 09 09:39:07 2020 -0500 |
| committer | GitHub <noreply@github.com> | Mon Nov 09 09:39:07 2020 -0500 |
| tree | 5ac9cfe595a1652b29adca31c54d1ffa30d4ac59 | |
| parent | 2517fa8538d616830340da4984502271fb902f19 [diff] | |
| parent | b9a8c9124aa967d55b8bde8fcdc6674f1b210082 [diff] |
Merge pull request #32 from dan-rodrigues/user_proj_wb_ack user_proj_example.v: Fix wbs_ack_o wiring
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index a72d99e..f1feed5 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -91,7 +91,7 @@ ) counter( .clk(clk), .reset(rst), - .ready(wbs_ack_i), + .ready(wbs_ack_o), .valid(valid), .rdata(rdata), .wdata(wbs_dat_i),