| commit | 496a08abbe49b76515a0f8f460467969beeb09e3 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 26 15:44:51 2020 -0400 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Wed Oct 28 22:58:29 2020 +0200 |
| tree | 2ad52c76c00e7cfe8ab315472f8734dcf0e9a93d | |
| parent | e1b1f176b368ad80c6cdce10f264982fee983851 [diff] |
Corrected an issue with the JTAG and SDO pins that prevented them from being converted to general purpose digital I/O signals by the management SoC. This was showing up in the timer testbench which was not seeing the low two output bits.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: