[DOC] more cleanups
diff --git a/README.md b/README.md
index 87210c6..9aa3f83 100644
--- a/README.md
+++ b/README.md
@@ -38,7 +38,7 @@
Then you need to install the open_pdks prerequisite:
- [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) is needed to run open_pdks -- version >= 8.3.60*
- > \* Note: You can avoid the need for the magic prerequisite by using the openlane docker to do the installation step in open_pdks. This could be done by cloning [openlane](https://github.com/efabless/openlane/tree/master) and running this [script](https://github.com/efabless/openlane/blob/master/travisCI/travisBuild.sh) in the openlane root directrory.
+ > \* Note: You can avoid the need for the magic prerequisite by using the openlane docker to do the installation step in open_pdks. This could be done by cloning [openlane](https://github.com/efabless/openlane/tree/master) and following the instructions given there to use the Makefile.
Install the required version of the PDK by running the following commands:
@@ -77,7 +77,7 @@
make
```
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect ~100 magic DRC violations with the current "development" state of caravel.
+This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect ~90 magic DRC violations with the current "development" state of caravel.
## Running Make using OpenLANE Magic
@@ -103,7 +103,7 @@
exit
```
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect ~100 magic DRC violations with the current "development" state of caravel.
+This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect ~90 magic DRC violations with the current "development" state of caravel.
## Required Directory Structure
diff --git a/openlane/README.md b/openlane/README.md
index eceecbd..49aad65 100644
--- a/openlane/README.md
+++ b/openlane/README.md
@@ -25,7 +25,7 @@
export OPENLANE_ROOT=<the absolute path to the openlane directory cloned or to be cloned>
```
-**NOTE:** rc6 and caravel are still WIP so expect to run into some issues when using it.
+**NOTE:** caravel is still a WIP so expect to run into some issues when using it.
If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane). Alternatively, you can clone and build openlane through:
```bash
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 182ed6b..4e5cc61 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -29,7 +29,6 @@
set ::env(DIE_AREA) "0 0 600 600"
set ::env(DESIGN_IS_CORE) 0
-
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
@@ -37,3 +36,6 @@
set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.15
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 53b8b7b..6e403b9 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -21,17 +21,23 @@
# User Configurations
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../verilog/rtl/user_project_wrapper.v"
+
+## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
set ::env(CLOCK_NET) "mprj.clk"
set ::env(CLOCK_PERIOD) "10"
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
+## Internal Macros
+### Macro Placement
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
@@ -57,6 +63,9 @@
set ::env(MAGIC_ZEROIZE_ORIGIN) 0
set ::env(MAGIC_WRITE_FULL_LEF) 1
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+
# Area Configurations. DON'T TOUCH.
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2920 3520"
@@ -76,11 +85,11 @@
set ::env(FP_PDN_CORE_RING_VOFFSET) 0
set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
-
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(RUN_CVC) 0
# Pin Configurations. DON'T TOUCH
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
