Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-016 / 32d05420a28fe54bb6f74ef0fa3fd5247be0c2bd
commit32d05420a28fe54bb6f74ef0fa3fd5247be0c2bd[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Mon Oct 19 19:43:52 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Mon Oct 19 19:43:52 2020 -0400
treebf803b34794a5bd077bfb13342765503fc7f5e29
parentb6dd152556ce2581f06758efc45c9b387bc4c4ab [diff]
Added two additional features:  (1) Timer chaining, which allows one
timer to be clocked from the output of the other, forming a 64-bit
timer, and (2) User power-good signal, memory-mapped so that the state
of the user's 1.8V power domain can be assessed (should have the same
for the 3.3V domains).  Also:  The routing of the PLL output and trap
and IRQ inputs was moved from the single gpio pin to additional bits
in the user space, and an additional output routing was made for the
secondary clock.
8 files changed
tree: bf803b34794a5bd077bfb13342765503fc7f5e29
  1. doc/
  2. mag/
  3. verilog/
  4. LICENSE
  5. README.md
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.