Version with flattened user_project_wrapper passed through magic
diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
index cf4e437..4c58210 100644
--- a/gds/caravel.gds.gz
+++ b/gds/caravel.gds.gz
Binary files differ
diff --git a/gds/caravel.mag b/gds/caravel.mag
index 202ce17..234a598 100644
--- a/gds/caravel.mag
+++ b/gds/caravel.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1612354468
+timestamp 1612384210
<< checkpaint >>
rect -1260 -1260 718860 1038860
<< metal1 >>
@@ -80750,187 +80750,187 @@
rect 459478 40175 459520 40411
rect 454976 40133 459520 40175
use user_id_programming user_id_value ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 656624 0 1 80926
box 0 0 7109 7077
use storage storage ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 52032 0 1 53156
box 0 0 88934 189234
use mgmt_core soc ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 210422 0 1 53602
box 0 0 430000 180000
use sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ../mag
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 137896 0 -1 51956
box -66 -83 5058 5000
use simple_por por ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 654176 0 -1 112880
box 25 11 11344 8338
use mgmt_protect mgmt_buffers ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 212180 0 1 246848
box -1586 -1605 201502 19557
use gpio_control_block gpio_control_bidir\[1\] ../mag
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 166200
box 0 0 33934 18344
use gpio_control_block gpio_control_bidir\[0\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 121000
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[36\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 245800
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[37\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 202600
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[2\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 211200
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[3\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 256400
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[33\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 375400
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[34\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 332200
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[35\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 289000
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[4\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 301400
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[5\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 346400
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[7\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 479800
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[6\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 391600
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[32\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 418600
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[31\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 546200
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[30\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 589400
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[29\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 632600
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[9\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 568800
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[8\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 523800
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[10\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 614000
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[28\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 675800
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[27\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 719000
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[26\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 762200
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[13\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 749200
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[12\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 704200
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[11\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 659000
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[25\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 805400
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[24\]
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 8567 0 1 931224
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[23\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 97200 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[22\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 148600 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[21\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 200000 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[20\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 251400 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[19\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 303000 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[18\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 353400 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[17\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 420800 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[16\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 497800 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[15\]
-timestamp 1612354468
+timestamp 1612384210
transform 0 1 549200 -1 0 1029747
box 0 0 33934 18344
use gpio_control_block gpio_control_in\[14\]
-timestamp 1612354468
+timestamp 1612384210
transform -1 0 708537 0 1 927600
box 0 0 33934 18344
use user_project_wrapper mprj ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 65308 0 1 278716
box -8576 -7506 592500 711442
use chip_io padframe ../mag
-timestamp 1612354468
+timestamp 1612384210
transform 1 0 0 0 1 0
box 0 0 717600 1037600
<< properties >>
diff --git a/gds/caravel.old.gds.gz b/gds/caravel.old.gds.gz
index bb1a563..24a4c79 100644
--- a/gds/caravel.old.gds.gz
+++ b/gds/caravel.old.gds.gz
Binary files differ
diff --git a/gds/sky130_drc.txt b/gds/sky130_drc.txt
index 12760b8..b38ada5 100644
--- a/gds/sky130_drc.txt
+++ b/gds/sky130_drc.txt
@@ -8,500 +8,728 @@
</tags>
<categories>
<category>
- <name>ct.1</name>
- <description>ct.1 : minimum/maximum width of mcon : 0.17um</description>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
<categories>
</categories>
</category>
<category>
- <name>ct.2</name>
- <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <name>dnwell.3</name>
+ <description>dnwell.3 : min. dnwell spacing : 6.3um</description>
<categories>
</categories>
</category>
<category>
- <name>ct.4</name>
- <description>ct.4 : mcon should covered by li</description>
+ <name>dnwell.4</name>
+ <description>dnwell.4 : dnwell must not overlap pnp</description>
<categories>
</categories>
</category>
<category>
- <name>m1.1</name>
- <description>m1.1 : min. m1 width : 0.14um</description>
+ <name>dnwell.5</name>
+ <description>p+ must not straddle dnwell</description>
<categories>
</categories>
</category>
<category>
- <name>m1.2</name>
- <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
<categories>
</categories>
</category>
<category>
- <name>m1.3ab</name>
- <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
<categories>
</categories>
</category>
<category>
- <name>m1.4</name>
- <description>m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <name>nwell.5</name>
+ <description>nwell.5 : min. nwell enclosing dnwell exempt unside uhvi : 0.4um</description>
<categories>
</categories>
</category>
<category>
- <name>m1.4a</name>
- <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <name>nwell.6</name>
+ <description>nwell.6 : min. dnwell enclosing nwell exempt unside uhvi : 1.03um</description>
<categories>
</categories>
</category>
<category>
- <name>m1.6</name>
- <description>m1.6 : min. m1 area : 0.083um²</description>
+ <name>nwell.7</name>
+ <description>nwell.7 : min. dnwell separation nwell : 4.5um</description>
<categories>
</categories>
</category>
<category>
- <name>m1.7</name>
- <description>m1.7 : min. m1 holes area : 0.14um²</description>
+ <name>pwbm</name>
+ <description>pwbm must be inside uhvi</description>
<categories>
</categories>
</category>
<category>
- <name>m1.5</name>
- <description>m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um</description>
+ <name>pwbm.4</name>
+ <description>pwbm.4 : dnwell inside uhvi must be enclosed by pwbm</description>
<categories>
</categories>
</category>
<category>
- <name>via.4c.5c</name>
- <description>via.4c.5c : m1 must enclose all via</description>
+ <name>pwdem.3</name>
+ <description>pwdem.3 : pwde must be inside pwbm</description>
<categories>
</categories>
</category>
<category>
- <name>via.1a</name>
- <description>via.1a : minimum/maximum width of via : 0.15um</description>
+ <name>pwdem.4</name>
+ <description>pwdem.4 : pwde must be inside uhvi</description>
<categories>
</categories>
</category>
<category>
- <name>via.1b</name>
- <description>via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um</description>
+ <name>pwdem.5</name>
+ <description>pwdem.5 : pwde must be inside dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.3</name>
+ <description>hvtp.3 : min. hvtp enclosure of pfet gate : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.4</name>
+ <description>hvtp.4 : min. hvtp spacing pfet gate: 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.5</name>
+ <description>hvtp.5 : min. hvtp area : 0.265um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1</name>
+ <description>lvtn.1 : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.3a</name>
+ <description>lvtn.3a : min. lvtn spacing to gate : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.3b</name>
+ <description>lvtn.3b : min. lvtn spacing to pfet s/d : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.4b</name>
+ <description>lvtn.4b : min. lvtn enclosing to gate : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.9</name>
+ <description>lvtn.9 : min. lvtn spacing hvtp : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.4b</name>
+ <description>lvtn.4b : min. lvtn enclosure of gate : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.12</name>
+ <description>lvtn.12 : min. lvtn spacing nwell inside areaid.ce : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.13</name>
+ <description>lvtn.13 : min. lvtn area : 0.265um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.x.3</name>
+ <description>ncm.x.3 : ncm must not overlap n+diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2</name>
+ <description>ncm.2 : min. ncm spacing manual merge if smaller : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.3</name>
+ <description>ncm.3 : min. ncm enclosure of p+diff : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.5</name>
+ <description>ncm.5 : min. ncm spacing lvtn diff : 0.23um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.6</name>
+ <description>ncm.6 : min. ncm spacing nfet : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.7</name>
+ <description>ncm.13 : min. ncm area : 0.265um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. difftap width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.2</name>
+ <description>difftap.2: min. gate (exempt areaid.sc) width : 0.42um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.2</name>
+ <description>difftap.2: min. gate inside areaid.sc width : 0.36um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.4</name>
+ <description>difftap.4 : min. tap bound by diffusion : 0.29um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.5</name>
+ <description>difftap.5 : min. tap bound by 2 diffusions : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.6</name>
+ <description>difftap.6 : diff and tap not allowed to extend beyong their abutting ege</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.7</name>
+ <description>difftap.7 : min. diff/tap spacing to non-coincident diff edge : 0.13um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.7</name>
+ <description>difftap.7 : min. diff/tap spacing to non-coincident tap edge : 0.13um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.8</name>
+ <description>difftap.8 : min. p+diff enclosure by nwell : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.9</name>
+ <description>difftap.9 : min. n+diff spacing to nwell : 0.34um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.10</name>
+ <description>difftap.10 : min. n+tap enclosure by nwell : 0.18um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.11</name>
+ <description>difftap.11 : min. p+tap spacing to nwell : 0.13um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
<categories>
</categories>
</category>
<category>
- <name>via.2</name>
- <description>via.2 : min. via spacing : 0.17um</description>
+ <name>tunm.3</name>
+ <description>tunm.3 : min. tunm beyond gate : 0.095um</description>
<categories>
</categories>
</category>
<category>
- <name>via.4a</name>
- <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <name>tunm.4</name>
+ <description>tunm.4 : min. tunm spacing to gate outside tunm: 0.095um</description>
<categories>
</categories>
</category>
<category>
- <name>via.4b</name>
- <description>via.4b : min. m1 enclosure of 0.23um via : 0.03um</description>
+ <name>tunm.5</name>
+ <description>tunm.5 : gate must not straddle tunm</description>
<categories>
</categories>
</category>
<category>
- <name>via1.5a</name>
- <description>via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um</description>
+ <name>tunm.6a</name>
+ <description>tunm.6a : tunm not allowed outside dnwell</description>
<categories>
</categories>
</category>
<category>
- <name>via1.5b</name>
- <description>via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um</description>
+ <name>tunm.7</name>
+ <description>tunm.7 : min. tunm area : 0.672um²</description>
<categories>
</categories>
</category>
<category>
- <name>m2.1</name>
- <description>m2.1 : min. m2 width : 0.14um</description>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.2</name>
- <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <name>poly.1b</name>
+ <description>poly.1b: min. lvtn gate width : 0.35um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.3ab</name>
- <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.6</name>
- <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <name>poly.3</name>
+ <description>poly.3 : min. poly resistor width : 0.33um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.7</name>
- <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <name>poly.4</name>
+ <description>poly.4 : min. poly on field spacing to diff : 0.075um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.via</name>
- <description>m2.via : m2 must enclose via</description>
+ <name>poly.5</name>
+ <description>poly.5 : min. poly on field spacing to tap : 0.055um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.4</name>
- <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <name>poly.6</name>
+ <description>poly.6 : min. gate spacing to tap : 0.3um</description>
<categories>
</categories>
</category>
<category>
- <name>m2.5</name>
- <description>m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um</description>
+ <name>poly.7</name>
+ <description>poly.7 : min. source/drain length : 0.25um</description>
<categories>
</categories>
</category>
<category>
- <name>via2</name>
- <description>via2 : m2 must enclose all via2</description>
+ <name>poly.8</name>
+ <description>poly.8 : min. poly extention gate (endcap) : 0.13um</description>
<categories>
</categories>
</category>
<category>
- <name>via2.1a</name>
- <description>via2.1a : minimum/maximum width of via2 : 0.2um</description>
+ <name>poly.9</name>
+ <description>poly.9 : min. poly resistor space to poly or diff/tap : 0.48um</description>
<categories>
</categories>
</category>
<category>
- <name>via2.1b</name>
- <description>via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um</description>
+ <name>poly.10</name>
+ <description>poly.10 : poly must not overlap diff corner</description>
<categories>
</categories>
</category>
<category>
- <name>via2.2</name>
- <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <name>poly.11</name>
+ <description>poly.11 : non 90 degree angle gate</description>
<categories>
</categories>
</category>
<category>
- <name>via2.4</name>
- <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <name>poly.12</name>
+ <description>poly.12 : poly must not overlap tap</description>
<categories>
</categories>
</category>
<category>
- <name>via2.4a</name>
- <description>via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um</description>
+ <name>poly.15</name>
+ <description>poly.15 : poly must not overlap diff resistor</description>
<categories>
</categories>
</category>
<category>
- <name>via2.5</name>
- <description>via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um</description>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
<categories>
</categories>
</category>
<category>
- <name>m3.1</name>
- <description>m3.1 : min. m3 width : 0.3um</description>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
<categories>
</categories>
</category>
<category>
- <name>m3.2</name>
- <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <name>rpm.3</name>
+ <description>rpm.3 : min. rpm enclosure of poly resistor : 0.2um</description>
<categories>
</categories>
</category>
<category>
- <name>m3.3ab</name>
- <description>m3.3ab : min. 3um.m3 spacing m3 : 0.4um</description>
+ <name>rpm.4</name>
+ <description>rpm.4 : min. psdm enclosure of poly resistor : 0.11um</description>
<categories>
</categories>
</category>
<category>
- <name>m3.6</name>
- <description>m3.6 : min. m2 area : 0.24um²</description>
+ <name>rpm.5</name>
+ <description>rpm.5 : min. npc enclosure of poly resistor : 0.095um</description>
<categories>
</categories>
</category>
<category>
- <name>m3.via2</name>
- <description>m3.via2 : m3 must enclose via2</description>
+ <name>rpm.6</name>
+ <description>rpm.6 : min. rpm spacing nsdm: 0.2um</description>
<categories>
</categories>
</category>
<category>
- <name>m3.4</name>
- <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <name>rpm.7</name>
+ <description>rpm.7 : min. rpm spacing poly: 0.2um</description>
<categories>
</categories>
</category>
<category>
- <name>via3</name>
- <description>via3 : m3 must enclose all via3</description>
+ <name>rpm.8</name>
+ <description>rpm.8 : poly must not straddle rpm</description>
<categories>
</categories>
</category>
<category>
- <name>via3.1a</name>
- <description>via3.1a : minimum/maximum width of via3 : 0.2um</description>
+ <name>rpm.9</name>
+ <description>rpm.9 : min. poly resistor spacing hvntm: 0.185um</description>
<categories>
</categories>
</category>
<category>
- <name>via3.1a</name>
- <description>via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um</description>
+ <name>rpm.10</name>
+ <description>rpm.107 : min. rpm spacing pwbm: na</description>
<categories>
</categories>
</category>
<category>
- <name>via3.2</name>
- <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <name>varac.1</name>
+ <description>varac.1: min. varac channel length : 0.18um</description>
<categories>
</categories>
</category>
<category>
- <name>via3.4</name>
- <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <name>varac.2</name>
+ <description>varac.2: min. varac channel wdth : 1.0um</description>
<categories>
</categories>
</category>
<category>
- <name>via3.5</name>
- <description>via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um</description>
+ <name>varac.3</name>
+ <description>varac.3: min. varac channel space to hvtp : 0.18um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.1</name>
- <description>nsm.1 : min. nsm width : 3.0um</description>
+ <name>varac.4</name>
+ <description>varac.4: min. varac channel space to licon on tap : 0.25um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.2</name>
- <description>nsm.2 : min. nsm spacing : 4.0um</description>
+ <name>varac.5</name>
+ <description>varac.5: min. nwell enclosure of poly overlapping varac channel : 0.15um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of diff : 3.0um</description>
+ <name>varac.6</name>
+ <description>varac.6: min. varac channel tap space to difftap : 0.27um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of tap : 3.0um</description>
+ <name>varac.7</name>
+ <description>varac.7: nwell overlapping varac channel must not overlap p+diff</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of poly : 3.0um</description>
+ <name>photo.2</name>
+ <description>photo.2 : minimum/maximum width of photodiode : 3.0um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of li : 3.0um</description>
+ <name>photo.3</name>
+ <description>photo.3 : mini. photodiode spacing : 5.0um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of m1 : 3.0um</description>
+ <name>photo.4</name>
+ <description>photo.4 : mini. photodiode spacing to dnwell : 5.3um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of m2 : 3.0um</description>
+ <name>photo.5.6</name>
+ <description>photo.5.6 : photodiode edges must coincide areaid.po and enclosed by dnwell</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of m3 : 3.0um</description>
+ <name>photo.7</name>
+ <description>photo.7 : photodiode must be enclosed by p+tap ring</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of m4 : 3.0um</description>
+ <name>photo.8</name>
+ <description>photo.8 : minimum/maximum width of nwell inside photodiode : 0.84um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of m5 : 3.0um</description>
+ <name>photo.9</name>
+ <description>photo.9 : minimum/maximum enclosure of nwell by photodiode : 1.08um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.4</name>
- <description>nsm.4 : min. nsm enclosure of cfom : 3.0um</description>
+ <name>photo.10</name>
+ <description>photo.10 : minimum/maximum width of tap inside photodiode : 0.41um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to diff : 1.0um</description>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to tap : 1.0um</description>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be mnually merge if less : 0.27um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to poly : 1.0um</description>
+ <name>npc.4</name>
+ <description>npc.4 : min. npc spacing to gate : 0.09um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to li : 1.0um</description>
+ <name>nsdm.1</name>
+ <description>nsdm.1 : min. nsdm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to m1 : 1.0um</description>
+ <name>psdm.1</name>
+ <description>psdm.1 : min. psdm width : 0.38um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to m2 : 1.0um</description>
+ <name>n/psdm.1</name>
+ <description>n/psdm.1 : min. nsdm spacing, should be mnually merge if less : 0.38um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to m3 : 1.0um</description>
+ <name>n/psdm.1</name>
+ <description>n/psdm.1 : min. psdm spacing, should be mnually merge if less : 0.38um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to m4 : 1.0um</description>
+ <name>n/psdm.5a</name>
+ <description>n/psdm.5a : min. n/psdm enclosure diff except butting edge : 0.125um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to m5 : 1.0um</description>
+ <name>n/psdm.5b</name>
+ <description>n/psdm.5b : min. n/psdm enclosure tap except butting edge : 0.125um</description>
<categories>
</categories>
</category>
<category>
- <name>nsm.3</name>
- <description>nsm.3 : min. nsm spacing to cfom : 1.0um</description>
+ <name>n/psdm.6</name>
+ <description>n/psdm.6 : min. n/psdm enclosure of butting edge : 0.0um</description>
<categories>
</categories>
</category>
<category>
- <name>m4.1</name>
- <description>m4.1 : min. m4 width : 0.3um</description>
+ <name>n/psdm.7</name>
+ <description>n/psdm.7 : min. nsdm diff spacing to psdm diff except butting edge : 0.13um</description>
<categories>
</categories>
</category>
<category>
- <name>m4.2</name>
- <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <name>n/psdm.8</name>
+ <description>n/psdm.8 : diff should be the opposite type of well/substrate underneath</description>
<categories>
</categories>
</category>
<category>
- <name>m4.4</name>
- <description>m4.4 : min. m2 area : 0.24um²</description>
+ <name>n/psdm.8</name>
+ <description>n/psdm.8 : tap should be the same type of well/substrate underneath</description>
<categories>
</categories>
</category>
<category>
- <name>m4.5ab</name>
- <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <name>tap and diff</name>
+ <description>tap and diff must not overlap</description>
<categories>
</categories>
</category>
<category>
- <name>m4.via3</name>
- <description>m4.via3 : m4 must enclose via3</description>
+ <name>n/psdm.10a</name>
+ <description>n/psdm.10a : min. nsdm area : 0.265um²</description>
<categories>
</categories>
</category>
<category>
- <name>m4.3</name>
- <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <name>n/psdm.10b</name>
+ <description>n/psdm.10b : min. psdm area : 0.265um²</description>
<categories>
</categories>
</category>
<category>
- <name>via4.1a</name>
- <description>via4.1a : minimum/maximum width of via4 : 0.8um</description>
+ <name>licon.1</name>
+ <description>licon.1 : minimum/maximum width of licon : 0.17um</description>
<categories>
</categories>
</category>
<category>
- <name>via4.2</name>
- <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <name>licon.1b/c</name>
+ <description>licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um</description>
<categories>
</categories>
</category>
<category>
- <name>via4.4</name>
- <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <name>licon.2</name>
+ <description>licon.2 : min. licon spacing : 0.17um</description>
<categories>
</categories>
</category>
<category>
- <name>via4</name>
- <description>via4 : m4 must enclose all via4</description>
+ <name>licon.2b</name>
+ <description>licon.2b : min. licon 0.19um edge on resistor spacing : 0.35um</description>
<categories>
</categories>
</category>
<category>
- <name>m5.1</name>
- <description>m5.1 : min. m5 width : 1.6um</description>
+ <name>licon.2c</name>
+ <description>licon.2c : min. licon 2.0um edge on resistor spacing : 0.51um</description>
<categories>
</categories>
</category>
<category>
- <name>m5.2</name>
- <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <name>licon.2d</name>
+ <description>licon.2d : min. licon on resistor spacing other licon : 0.51um</description>
<categories>
</categories>
</category>
<category>
- <name>m5.via4</name>
- <description>m5.via4 : m5 must enclose via4</description>
+ <name>licon.4</name>
+ <description>licon.4 : min. licon must overlap li and (poly or tap or diff) </description>
<categories>
</categories>
</category>
<category>
- <name>m5.3</name>
- <description>m4.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <name>licon.5</name>
+ <description>licon.5 : min. diff enclosure of licon : 0.04um</description>
<categories>
</categories>
</category>
<category>
- <name>pad.2</name>
- <description>pad.2 : min. pad spacing : 1.27um</description>
+ <name>licon.6</name>
+ <description>licon.6 : min. abutting edge spacing to licon tap : 0.06um</description>
<categories>
</categories>
</category>
@@ -513,68 +741,21104 @@
<references>
</references>
</cell>
- <cell>
- <name>amsat_txrx_ic-caravel</name>
- <variant/>
- <references>
- <ref>
- <parent>user_project_wrapper</parent>
- <trans>r0 *1 2274.178,2.4</trans>
- </ref>
- </references>
- </cell>
- <cell>
- <name>pll_collection</name>
- <variant/>
- <references>
- <ref>
- <parent>user_project_wrapper</parent>
- <trans>r0 *1 -23.816,2.846</trans>
- </ref>
- </references>
- </cell>
- <cell>
- <name>vco_2-4GHz</name>
- <variant/>
- <references>
- <ref>
- <parent>user_project_wrapper</parent>
- <trans>r0 *1 334.871,2702.868</trans>
- </ref>
- </references>
- </cell>
- <cell>
- <name>vco_2-4GHz_powertap</name>
- <variant/>
- <references>
- <ref>
- <parent>user_project_wrapper</parent>
- <trans>r0 *1 362.746,2730.868</trans>
- </ref>
- </references>
- </cell>
</cells>
<items>
<item>
<tags/>
- <category>'m3.3ab'</category>
- <cell>vco_2-4GHz_powertap</cell>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<image/>
<values>
- <value>edge-pair: (4.81,3.545;5.448,3.545)/(5.19,3.851;4.81,3.851)</value>
+ <value>edge-pair: (2373.405,2853.33;2373.405,2855.78)/(2375.855,2855.78;2375.855,2853.33)</value>
</values>
</item>
<item>
<tags/>
- <category>'m3.3ab'</category>
- <cell>vco_2-4GHz_powertap</cell>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
<visited>false</visited>
<multiplicity>1</multiplicity>
<image/>
<values>
- <value>edge-pair: (4.81,3.545;5.349,3.545)/(5.185,3.91;4.815,3.91)</value>
+ <value>edge-pair: (2373.405,2855.78;2375.855,2855.78)/(2375.855,2853.33;2373.405,2853.33)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2373.405,2849.61;2373.405,2852.06)/(2375.855,2852.06;2375.855,2849.61)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2373.405,2852.06;2375.855,2852.06)/(2375.855,2849.61;2373.405,2849.61)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2373.405,2845.89;2373.405,2848.34)/(2375.855,2848.34;2375.855,2845.89)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2373.405,2848.34;2375.855,2848.34)/(2375.855,2845.89;2373.405,2845.89)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2369.685,2845.89;2369.685,2848.34)/(2372.135,2848.34;2372.135,2845.89)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2369.685,2848.34;2372.135,2848.34)/(2372.135,2845.89;2369.685,2845.89)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2369.685,2849.61;2369.685,2852.06)/(2372.135,2852.06;2372.135,2849.61)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2369.685,2852.06;2372.135,2852.06)/(2372.135,2849.61;2369.685,2849.61)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2369.685,2853.33;2369.685,2855.78)/(2372.135,2855.78;2372.135,2853.33)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2369.685,2855.78;2372.135,2855.78)/(2372.135,2853.33;2369.685,2853.33)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>edge-pair: (2365.965,2845.89;2365.965,2848.34)/(2368.415,2848.34;2368.415,2845.89)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'dnwell.2'</category>
+ <cell>user_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
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diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 8f93666..6a7d3c6 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper_klayout.gds.gz b/gds/user_project_wrapper_klayout.gds.gz
new file mode 100644
index 0000000..6841cd8
--- /dev/null
+++ b/gds/user_project_wrapper_klayout.gds.gz
Binary files differ
