commit	055375111fc49797ccf31971f17be971c29b1925	[log] [tgz]
author	Tim Edwards <tim@opencircuitdesign.com>	Tue Oct 06 14:59:26 2020 -0400
committer	Tim Edwards <tim@opencircuitdesign.com>	Tue Oct 06 14:59:26 2020 -0400
tree	1fd4a48384ee16058814326ca46c3a05b982a23a
parent	ca2f318bb428801e0739cc341d80def2d8c70559 [diff]

Most testbenches are working again now.  Renamed "mprj_counter" to "user_proj_example"
and made the filename equal to the module name, for clarity.

verilog/dv/README.md[diff]
verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c[diff]
verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v[diff]
verilog/dv/caravel/mgmt_soc/uart/uart_tb.v[diff]
verilog/dv/caravel/mprj_counter/io_ports/Makefile[Deleted - diff]
verilog/dv/caravel/mprj_counter/io_ports/io_ports.c[Deleted - diff]
verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/caravel/mprj_counter/la_test1/Makefile[Deleted - diff]
verilog/dv/caravel/mprj_counter/la_test1/la_test1.c[Deleted - diff]
verilog/dv/caravel/mprj_counter/la_test2/Makefile[Deleted - diff]
verilog/dv/caravel/mprj_counter/la_test2/la_test2.c[Deleted - diff]
verilog/dv/caravel/user_proj_example/Makefile[Renamed from verilog/dv/caravel/mprj_counter/Makefile - diff]
verilog/dv/caravel/user_proj_example/README.md[Renamed from verilog/dv/caravel/mprj_counter/README.md - diff]
verilog/dv/caravel/user_proj_example/io_ports/Makefile[Added - diff]
verilog/dv/caravel/user_proj_example/io_ports/io_ports.c[Added - diff]
verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/caravel/user_proj_example/la_test1/Makefile[Added - diff]
verilog/dv/caravel/user_proj_example/la_test1/la_test1.c[Added - diff]
verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v[Renamed from verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v - diff]
verilog/dv/caravel/user_proj_example/la_test2/Makefile[Added - diff]
verilog/dv/caravel/user_proj_example/la_test2/la_test2.c[Added - diff]
verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v[Renamed from verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v - diff]
verilog/rtl/caravel.v[diff]
verilog/rtl/mprj_ctrl.v.orig[Deleted - diff]
verilog/rtl/user_proj_example.v[Renamed from verilog/rtl/mprj_counter.v - diff]

25 files changed

tree: 1fd4a48384ee16058814326ca46c3a05b982a23a

README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

Configure Mega Project I/O pads
Observe and control Mega Project signals (through on-chip logic analyzer probes)
Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.