README.md - third_party/shuttle/sky130/mpw-001/slot-015 - Git at Google

 # CIIC Harness

 A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

 <p align=”center”>
 <img src="/doc/ciic_harness.png" width="75%" height="75%">
 </p>

 ## Getting Started:

 Start by cloning the repo and uncompressing the files.
 ```bash
 git clone https://github.com/efabless/caravel.git
 cd caravel
 make uncompress
 ```

 Then, you can learn more about the caravel chip by watching these video:
 - Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
 - Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
 - Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw

 ## Managment SoC
 The managment SoC runs firmware that can be used to:
 - Configure Mega Project I/O pads
 - Observe and control Mega Project signals (through on-chip logic analyzer probes)
 - Control the Mega Project power supply

 The memory map of the management SoC can be found [here](verilog/rtl/README)

 ## Mega Project Area
 This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10).  See [the Caravel  premliminary datasheet](doc/caravel_datasheet.pdf) for details.
 The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter.  </br>

 <p align=”center”>
 <img src="/doc/counter_32.png" width="50%" height="50%">
 </p>

 The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
 1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
 2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
 3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles:  [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
	# CIIC Harness

	A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

	<p align=”center”>
	<img src="/doc/ciic_harness.png" width="75%" height="75%">
	</p>

	## Getting Started:

	Start by cloning the repo and uncompressing the files.
	```bash
	git clone https://github.com/efabless/caravel.git
	cd caravel
	make uncompress
	```

	Then, you can learn more about the caravel chip by watching these video:
	- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
	- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
	- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw

	## Managment SoC
	The managment SoC runs firmware that can be used to:
	- Configure Mega Project I/O pads
	- Observe and control Mega Project signals (through on-chip logic analyzer probes)
	- Control the Mega Project power supply

	The memory map of the management SoC can be found [here](verilog/rtl/README)

	## Mega Project Area
	This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel_datasheet.pdf) for details.
	The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>

	<p align=”center”>
	<img src="/doc/counter_32.png" width="50%" height="50%">
	</p>

	The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
	1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
	2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
	3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).