Update openlane configs
- of caravel, chip_io, user_project_wrapper to suit the new dimensions
diff --git a/openlane/caravel/interactive.tcl b/openlane/caravel/interactive.tcl
index 7d3e72c..c98041e 100755
--- a/openlane/caravel/interactive.tcl
+++ b/openlane/caravel/interactive.tcl
@@ -10,20 +10,19 @@
init_floorplan
add_macro_placement padframe 0 0 N
-add_macro_placement storage 279.960 219.360 N
-add_macro_placement soc 813.755 226.905 N
-add_macro_placement mprj 251.520 1279.800 N
-add_macro_placement mgmt_buffers 887.200 1158.940 N
-add_macro_placement porb_level 778.715 1099.725 N
-add_macro_placement rstb_level 826.125 1099.725 N
+add_macro_placement storage 280.650 263.920 N
+add_macro_placement soc 814.445 274.435 N
+add_macro_placement mprj 374.750 1279.800 N
+add_macro_placement mgmt_buffers 887.890 1158.940 N
+add_macro_placement rstb_level 826.815 1163.920 N
add_macro_placement user_id_value 778.715 1158.940 N
-add_macro_placement por 2903.225 2184.205 N
+add_macro_placement por 2943.930 1167.355 N
# west
# gpio_control_blocks: 37 ... 32
-set x 38.560
-set y 1119.130
-set pitch 227
+set x 39.250
+set y 1090.740
+set pitch 223
set orient N
for {set i 37} {$i >= 32} {incr i -1} {
add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient
@@ -43,9 +42,9 @@
# east
# gpio_control_bidir: 0 ... 1
-set x 3111.080
-set y 696.300
-set pitch 238
+set x 3488.340
+set y 675.680
+set pitch 233
set orient N; # mirror
for {set i 0} {$i <= 1} {incr i} {
add_macro_placement "gpio_control_bidir\\\[$i\\\]" $x $y $orient
@@ -71,9 +70,9 @@
# north
# gpio_control_in: 23 ... 15
-set x 468.460
-set y 5207.760
-set pitch 241
+set x 509.535
+set y 5093
+set pitch 273
set orient R270
for {set i 23} {$i >= 15} {incr i -1} {
add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient
@@ -83,6 +82,11 @@
manual_macro_placement f
+# li1_hack_start
+# global_routing
+# detailed_routing
+# li1_hack_end
+
run_magic
save_views -lef_path $::env(magic_result_file_tag).lef \
diff --git a/openlane/chip_io/config.tcl b/openlane/chip_io/config.tcl
index 6396c77..9a2145a 100644
--- a/openlane/chip_io/config.tcl
+++ b/openlane/chip_io/config.tcl
@@ -16,6 +16,12 @@
set ::env(USE_GPIO_PADS) 1
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 3200 5300"
+set ::env(DIE_AREA) "0 0 3588 5188"
+
set ::env(MAGIC_WRITE_FULL_LEF) 1
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(GLB_RT_TILES) 20
+set ::env(GLB_RT_UNIDIRECTIONAL) 0
+# set ::env(GLB_RT_ALLOW_CONGESTION) 1
diff --git a/openlane/chip_io/interactive.tcl b/openlane/chip_io/interactive.tcl
index 05ae7a1..2529819 100644
--- a/openlane/chip_io/interactive.tcl
+++ b/openlane/chip_io/interactive.tcl
@@ -4,6 +4,12 @@
prep -design $script_dir -tag chip_io -overwrite
set save_path $script_dir/../..
+# set ::env(SYNTH_DEFINES) ""
+# verilog_elaborate
+# init_floorplan
+# file copy $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
+
+set ::env(SYNTH_DEFINES) "TOP_ROUTING"
verilog_elaborate
init_floorplan
@@ -18,30 +24,52 @@
set_def $::env(RESULTS_DIR)/floorplan/padframe.def
+# modify to a different file
+remove_pins -input $::env(CURRENT_DEF)
-label_macro_pins\
- -lef $::env(MERGED_LEF_UNPADDED)\
- -netlist_def $::env(CURRENT_DEF)\
- -pad_pin_name "PAD"\
- -extra_args {-v\
- --map mgmt_vdda_hvclamp_pad VDDA vdda INOUT\
- --map user1_vdda_hvclamp_pad\\\[0\\] VDDA vdda1 INOUT\
- --map user2_vdda_hvclamp_pad VDDA vdda2 INOUT\
- --map mgmt_vssa_hvclamp_pad VSSA vssa INOUT\
- --map user1_vssa_hvclamp_pad\\\[0\\] VSSA vssa1 INOUT\
- --map user2_vssa_hvclamp_pad VSSA vssa2 INOUT\
- --map mgmt_vccd_lvclamp_pad VCCD vccd INOUT\
- --map user1_vccd_lvclamp_pad VCCD vccd1 INOUT\
- --map user2_vccd_lvclamp_pad VCCD vccd2 INOUT\
- --map mgmt_vssd_lvclmap_pad VSSD vssd INOUT\
- --map user1_vssd_lvclmap_pad VSSD vssd1 INOUT\
- --map user2_vssd_lvclmap_pad VSSD vssd2 INOUT\
- --map mgmt_vddio_hvclamp_pad\\\[0\\] VDDIO vddio INOUT\
- --map mgmt_vssio_hvclamp_pad\\\[0\\] VSSIO vssio INOUT}
+remove_empty_nets -input $::env(CURRENT_DEF)
+
+add_macro_obs \
+ -defFile $::env(CURRENT_DEF) \
+ -lefFile $::env(MERGED_LEF_UNPADDED) \
+ -obstruction core_obs \
+ -placementX 500 \
+ -placementY 500 \
+ -sizeWidth 2200 \
+ -sizeHeight 4300 \
+ -fixed 1 \
+ -layerNames "met1 met2 met3 met4 met5"
+
+
+li1_hack_start
+global_routing
+detailed_routing
+li1_hack_end
+
+# label_macro_pins\
+# -lef $::env(MERGED_LEF_UNPADDED)\
+# -netlist_def $::env(CURRENT_DEF)\
+# -pad_pin_name "PAD"\
+# -extra_args {-v\
+# --map mgmt_vdda_hvclamp_pad VDDA vdda INOUT\
+# --map user1_vdda_hvclamp_pad\\\[0\\] VDDA vdda1 INOUT\
+# --map user2_vdda_hvclamp_pad VDDA vdda2 INOUT\
+# --map mgmt_vssa_hvclamp_pad VSSA vssa INOUT\
+# --map user1_vssa_hvclamp_pad\\\[0\\] VSSA vssa1 INOUT\
+# --map user2_vssa_hvclamp_pad VSSA vssa2 INOUT\
+# --map mgmt_vccd_lvclamp_pad VCCD vccd INOUT\
+# --map user1_vccd_lvclamp_pad VCCD vccd1 INOUT\
+# --map user2_vccd_lvclamp_pad VCCD vccd2 INOUT\
+# --map mgmt_vssd_lvclmap_pad VSSD vssd INOUT\
+# --map user1_vssd_lvclmap_pad VSSD vssd1 INOUT\
+# --map user2_vssd_lvclmap_pad VSSD vssd2 INOUT\
+# --map mgmt_vddio_hvclamp_pad\\\[0\\] VDDIO vddio INOUT\
+# --map mgmt_vssio_hvclamp_pad\\\[0\\] VSSIO vssio INOUT}
+
run_magic
-run_magic_drc
+# run_magic_drc
save_views -lef_path $::env(magic_result_file_tag).lef \
-def_path $::env(CURRENT_DEF) \
@@ -51,5 +79,5 @@
-tag $::env(RUN_TAG)
-run_magic_spice_export
-run_lvs
+# run_magic_spice_export
+# run_lvs
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 5528fc9..20eb097 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -10,6 +10,12 @@
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 250 250"
+set ::env(DIE_AREA) "0 0 600 600"
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+# set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
+# set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
+
set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.15
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e026680..50e0bd1 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -8,10 +8,12 @@
set ::env(CLOCK_PERIOD) "10"
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2700 3700"
-set ::env(PL_TARGET_DENSITY) 0.001
+set ::env(DIE_AREA) "0 0 2920 3520"
set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v \
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 1f554c1..dd5c0d1 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -8,12 +8,14 @@
init_floorplan
-place_io
+place_io_ol
-add_macro_placement mprj 1355 3000 N
+add_macro_placement mprj 1150 1700 N
manual_macro_placement f
+gen_pdn
+
global_routing_or
detailed_routing
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl
new file mode 100644
index 0000000..4fe8996
--- /dev/null
+++ b/openlane/user_project_wrapper/pdn.tcl
@@ -0,0 +1,42 @@
+# Power nets
+set ::power_nets vccd1
+set ::ground_nets vssd1
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+ name grid
+ core_ring {
+ met5 {width 2 spacing 2 core_offset 3}
+ met4 {width 2 spacing 2 core_offset 3}
+ }
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ }
+ connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+ power_pins "VPWR"
+ ground_pins "VGND"
+ blockages "li1 met1 met2 met3 met4"
+ straps {
+ }
+ connect {{met4_PIN_ver met5}}
+}
+
+
+set ::halo 0
+
+# Metal layer for rails on every row
+set ::rails_mlayer "met1" ;
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
