| commit | b6dd152556ce2581f06758efc45c9b387bc4c4ab | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 19 15:58:25 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 19 15:58:25 2020 -0400 |
| tree | 77f58827c6d18bbb87dff16e4cffc8ad415fa1c1 | |
| parent | 268a90bd2da91eba601fe9f9e6de573bbe272951 [diff] |
Updated testbenches to declare 38 bits for the user project GPIO pins.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)
This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: