| $date |
| Fri Aug 21 14:21:19 2020 |
| $end |
| $version |
| Icarus Verilog |
| $end |
| $timescale |
| 1ps |
| $end |
| $scope module sysctrl_wb_tb $end |
| $var wire 32 ! irq7_src_adr [31:0] $end |
| $var wire 32 " irq8_src_adr [31:0] $end |
| $var wire 32 # osc_ena_adr [31:0] $end |
| $var wire 32 $ osc_out_adr [31:0] $end |
| $var wire 32 % overtemp_adr [31:0] $end |
| $var wire 32 & overtemp_ena_adr [31:0] $end |
| $var wire 32 ' ovetemp_out_adr [31:0] $end |
| $var wire 32 ( pll_out_adr [31:0] $end |
| $var wire 32 ) trap_out_adr [31:0] $end |
| $var wire 32 * xtal_out_adr [31:0] $end |
| $var wire 32 + wb_dat_o [31:0] $end |
| $var wire 1 , wb_ack_o $end |
| $var reg 2 - irq_7_inputsrc [1:0] $end |
| $var reg 2 . irq_8_inputsrc [1:0] $end |
| $var reg 1 / overtemp $end |
| $var reg 2 0 overtemp_dest [1:0] $end |
| $var reg 1 1 overtemp_ena $end |
| $var reg 2 2 pll_output_dest [1:0] $end |
| $var reg 1 3 rcosc_ena $end |
| $var reg 2 4 rcosc_output_dest [1:0] $end |
| $var reg 2 5 trap_output_dest [1:0] $end |
| $var reg 32 6 wb_adr_i [31:0] $end |
| $var reg 1 7 wb_clk_i $end |
| $var reg 1 8 wb_cyc_i $end |
| $var reg 32 9 wb_dat_i [31:0] $end |
| $var reg 1 : wb_rst_i $end |
| $var reg 4 ; wb_sel_i [3:0] $end |
| $var reg 1 < wb_stb_i $end |
| $var reg 1 = wb_we_i $end |
| $var reg 2 > xtal_output_dest [1:0] $end |
| $scope module uut $end |
| $var wire 4 ? iomem_we [3:0] $end |
| $var wire 1 / overtemp $end |
| $var wire 1 @ resetn $end |
| $var wire 1 A valid $end |
| $var wire 1 , wb_ack_o $end |
| $var wire 32 B wb_adr_i [31:0] $end |
| $var wire 1 7 wb_clk_i $end |
| $var wire 1 8 wb_cyc_i $end |
| $var wire 32 C wb_dat_i [31:0] $end |
| $var wire 1 : wb_rst_i $end |
| $var wire 4 D wb_sel_i [3:0] $end |
| $var wire 1 < wb_stb_i $end |
| $var wire 1 = wb_we_i $end |
| $var wire 2 E xtal_output_dest [1:0] $end |
| $var wire 32 F wb_dat_o [31:0] $end |
| $var wire 2 G trap_output_dest [1:0] $end |
| $var wire 1 H ready $end |
| $var wire 2 I rcosc_output_dest [1:0] $end |
| $var wire 1 J rcosc_ena $end |
| $var wire 2 K pll_output_dest [1:0] $end |
| $var wire 1 L overtemp_ena $end |
| $var wire 2 M overtemp_dest [1:0] $end |
| $var wire 2 N irq_8_inputsrc [1:0] $end |
| $var wire 2 O irq_7_inputsrc [1:0] $end |
| $scope module sysctrl $end |
| $var wire 1 7 clk $end |
| $var wire 32 P iomem_addr [31:0] $end |
| $var wire 1 A iomem_valid $end |
| $var wire 32 Q iomem_wdata [31:0] $end |
| $var wire 4 R iomem_wstrb [3:0] $end |
| $var wire 1 / overtemp $end |
| $var wire 1 @ resetn $end |
| $var wire 1 S xtal_out_sel $end |
| $var wire 1 T trap_out_sel $end |
| $var wire 1 U pll_out_sel $end |
| $var wire 1 V overtemp_sel $end |
| $var wire 1 W overtemp_ena_sel $end |
| $var wire 1 X overtemp_dest_sel $end |
| $var wire 1 Y osc_out_sel $end |
| $var wire 1 Z osc_ena_sel $end |
| $var wire 1 [ irq8_sel $end |
| $var wire 1 \ irq7_sel $end |
| $var reg 32 ] iomem_rdata [31:0] $end |
| $var reg 1 H iomem_ready $end |
| $var reg 2 ^ irq_7_inputsrc [1:0] $end |
| $var reg 2 _ irq_8_inputsrc [1:0] $end |
| $var reg 2 ` overtemp_dest [1:0] $end |
| $var reg 1 L overtemp_ena $end |
| $var reg 2 a pll_output_dest [1:0] $end |
| $var reg 1 J rcosc_ena $end |
| $var reg 2 b rcosc_output_dest [1:0] $end |
| $var reg 2 c trap_output_dest [1:0] $end |
| $var reg 2 d xtal_output_dest [1:0] $end |
| $upscope $end |
| $upscope $end |
| $scope task read $end |
| $var reg 33 e addr [32:0] $end |
| $upscope $end |
| $scope task write $end |
| $var reg 33 f addr [32:0] $end |
| $var reg 33 g data [32:0] $end |
| $upscope $end |
| $upscope $end |
| $enddefinitions $end |
| #0 |
| $dumpvars |
| bx g |
| bx f |
| bx e |
| bx d |
| bx c |
| bx b |
| bx a |
| bx ` |
| bx _ |
| bx ^ |
| bx ] |
| 0\ |
| 0[ |
| 1Z |
| 0Y |
| 0X |
| 0W |
| 0V |
| 0U |
| 0T |
| 0S |
| b0 R |
| b0 Q |
| b0 P |
| bx O |
| bx N |
| bx M |
| xL |
| bx K |
| xJ |
| bx I |
| xH |
| bx G |
| bx F |
| bx E |
| b0 D |
| b0 C |
| b0 B |
| 0A |
| 0@ |
| b0 ? |
| bx > |
| 0= |
| 0< |
| b0 ; |
| 1: |
| b0 9 |
| 08 |
| 07 |
| b0 6 |
| bx 5 |
| bx 4 |
| x3 |
| bx 2 |
| x1 |
| bx 0 |
| x/ |
| bx . |
| bx - |
| x, |
| bx + |
| b101111000000000000000000001000 * |
| b101111000000000000000000010000 ) |
| b101111000000000000000000001100 ( |
| b101111000000000000000000100100 ' |
| b101111000000000000000000011100 & |
| b101111000000000000000000100000 % |
| b101111000000000000000000000100 $ |
| b101111000000000000000000000000 # |
| b101111000000000000000000011000 " |
| b101111000000000000000000010100 ! |
| $end |
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| b0 d |
| b0 K |
| b0 a |
| b0 I |
| b0 b |
| 0J |
| 17 |
| #2000 |
| 1@ |
| 07 |
| 0: |
| #3000 |
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| 0H |
| 17 |
| #4000 |
| 07 |
| b1 g |
| b101111000000000000000000000000 f |
| b1 0 |
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| b11 . |
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| b10 5 |
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| b1 > |
| b10 4 |
| 13 |
| 1/ |
| #5000 |
| b1111 ? |
| b1111 R |
| 1A |
| b1 9 |
| b1 C |
| b1 Q |
| b101111000000000000000000000000 6 |
| b101111000000000000000000000000 B |
| b101111000000000000000000000000 P |
| 1= |
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| 1< |
| 17 |
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| 07 |
| #7000 |
| 1J |
| b0 + |
| b0 F |
| b0 ] |
| 1, |
| 1H |
| 17 |
| #8000 |
| 07 |
| #9000 |
| 0A |
| b10 g |
| b101111000000000000000000000100 f |
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| 1Y |
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| b10 Q |
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| b10 I |
| b10 b |
| 1, |
| 1H |
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| 0A |
| b1 g |
| b101111000000000000000000001000 f |
| 0< |
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| 0, |
| 0H |
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| 07 |
| #17000 |
| 0Y |
| 1S |
| 1A |
| b1 9 |
| b1 C |
| b1 Q |
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| b101111000000000000000000001000 B |
| b101111000000000000000000001000 P |
| 18 |
| 1< |
| 17 |
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| b1 E |
| b1 d |
| 1, |
| 1H |
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| b11 g |
| b101111000000000000000000001100 f |
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| 1U |
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| 1A |
| b11 9 |
| b11 C |
| b11 Q |
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| b101111000000000000000000001100 B |
| b101111000000000000000000001100 P |
| 18 |
| 1< |
| 17 |
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| b11 K |
| b11 a |
| 1, |
| 1H |
| 17 |
| #26000 |
| 07 |
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| 0A |
| b10 g |
| b101111000000000000000000010000 f |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #28000 |
| 07 |
| #29000 |
| 0U |
| 1T |
| 1A |
| b10 9 |
| b10 C |
| b10 Q |
| b101111000000000000000000010000 6 |
| b101111000000000000000000010000 B |
| b101111000000000000000000010000 P |
| 18 |
| 1< |
| 17 |
| #30000 |
| 07 |
| #31000 |
| b10 G |
| b10 c |
| 1, |
| 1H |
| 17 |
| #32000 |
| 07 |
| #33000 |
| 0A |
| b1 g |
| b101111000000000000000000010100 f |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #34000 |
| 07 |
| #35000 |
| 0T |
| 1\ |
| 1A |
| b1 9 |
| b1 C |
| b1 Q |
| b101111000000000000000000010100 6 |
| b101111000000000000000000010100 B |
| b101111000000000000000000010100 P |
| 18 |
| 1< |
| 17 |
| #36000 |
| 07 |
| #37000 |
| b1 O |
| b1 ^ |
| 1, |
| 1H |
| 17 |
| #38000 |
| 07 |
| #39000 |
| 0A |
| b11 g |
| b101111000000000000000000011000 f |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #40000 |
| 07 |
| #41000 |
| 0\ |
| 1[ |
| 1A |
| b11 9 |
| b11 C |
| b11 Q |
| b101111000000000000000000011000 6 |
| b101111000000000000000000011000 B |
| b101111000000000000000000011000 P |
| 18 |
| 1< |
| 17 |
| #42000 |
| 07 |
| #43000 |
| b11 N |
| b11 _ |
| 1, |
| 1H |
| 17 |
| #44000 |
| 07 |
| #45000 |
| 0A |
| b1 g |
| b101111000000000000000000011100 f |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #46000 |
| 07 |
| #47000 |
| 0[ |
| 1W |
| 1A |
| b1 9 |
| b1 C |
| b1 Q |
| b101111000000000000000000011100 6 |
| b101111000000000000000000011100 B |
| b101111000000000000000000011100 P |
| 18 |
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| 1, |
| 1H |
| 17 |
| #50000 |
| 07 |
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| 0H |
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| 07 |
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| 0W |
| 1X |
| 1A |
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| 18 |
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| b1 M |
| b1 ` |
| 1, |
| 1H |
| 17 |
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| 07 |
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| 0A |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #58000 |
| 07 |
| #59000 |
| 1V |
| 0X |
| b0 ? |
| b0 R |
| 1A |
| b101111000000000000000000100000 6 |
| b101111000000000000000000100000 B |
| b101111000000000000000000100000 P |
| 0= |
| 18 |
| 1< |
| 17 |
| b101111000000000000000000100000 e |
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| 07 |
| #61000 |
| b1 + |
| b1 F |
| b1 ] |
| 1, |
| 1H |
| 17 |
| #62000 |
| 07 |
| #63000 |
| 0A |
| b101111000000000000000000000000 e |
| 0< |
| 08 |
| 0, |
| 0H |
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| 07 |
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| 1Z |
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| 1A |
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| 18 |
| 1< |
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| 07 |
| #67000 |
| 1, |
| 1H |
| 17 |
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| 07 |
| #69000 |
| 0A |
| b101111000000000000000000000100 e |
| 0< |
| 08 |
| 0, |
| 0H |
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| 07 |
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| 1Y |
| 1A |
| b101111000000000000000000000100 6 |
| b101111000000000000000000000100 B |
| b101111000000000000000000000100 P |
| 18 |
| 1< |
| 17 |
| #72000 |
| 07 |
| #73000 |
| b10 + |
| b10 F |
| b10 ] |
| 1, |
| 1H |
| 17 |
| #74000 |
| 07 |
| #75000 |
| 0A |
| b101111000000000000000000001000 e |
| 0< |
| 08 |
| 0, |
| 0H |
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| #76000 |
| 07 |
| #77000 |
| 0Y |
| 1S |
| 1A |
| b101111000000000000000000001000 6 |
| b101111000000000000000000001000 B |
| b101111000000000000000000001000 P |
| 18 |
| 1< |
| 17 |
| #78000 |
| 07 |
| #79000 |
| b1 + |
| b1 F |
| b1 ] |
| 1, |
| 1H |
| 17 |
| #80000 |
| 07 |
| #81000 |
| 0A |
| b101111000000000000000000001100 e |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #82000 |
| 07 |
| #83000 |
| 1U |
| 0S |
| 1A |
| b101111000000000000000000001100 6 |
| b101111000000000000000000001100 B |
| b101111000000000000000000001100 P |
| 18 |
| 1< |
| 17 |
| #84000 |
| 07 |
| #85000 |
| b11 + |
| b11 F |
| b11 ] |
| 1, |
| 1H |
| 17 |
| #86000 |
| 07 |
| #87000 |
| 0A |
| b101111000000000000000000010000 e |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #88000 |
| 07 |
| #89000 |
| 0U |
| 1T |
| 1A |
| b101111000000000000000000010000 6 |
| b101111000000000000000000010000 B |
| b101111000000000000000000010000 P |
| 18 |
| 1< |
| 17 |
| #90000 |
| 07 |
| #91000 |
| b10 + |
| b10 F |
| b10 ] |
| 1, |
| 1H |
| 17 |
| #92000 |
| 07 |
| #93000 |
| 0A |
| b101111000000000000000000010100 e |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #94000 |
| 07 |
| #95000 |
| 0T |
| 1\ |
| 1A |
| b101111000000000000000000010100 6 |
| b101111000000000000000000010100 B |
| b101111000000000000000000010100 P |
| 18 |
| 1< |
| 17 |
| #96000 |
| 07 |
| #97000 |
| b1 + |
| b1 F |
| b1 ] |
| 1, |
| 1H |
| 17 |
| #98000 |
| 07 |
| #99000 |
| 0A |
| b101111000000000000000000011000 e |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #100000 |
| 07 |
| #101000 |
| 0\ |
| 1[ |
| 1A |
| b101111000000000000000000011000 6 |
| b101111000000000000000000011000 B |
| b101111000000000000000000011000 P |
| 18 |
| 1< |
| 17 |
| #102000 |
| 07 |
| #103000 |
| b11 + |
| b11 F |
| b11 ] |
| 1, |
| 1H |
| 17 |
| #104000 |
| 07 |
| #105000 |
| 0A |
| b101111000000000000000000011100 e |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #106000 |
| 07 |
| #107000 |
| 0[ |
| 1W |
| 1A |
| b101111000000000000000000011100 6 |
| b101111000000000000000000011100 B |
| b101111000000000000000000011100 P |
| 18 |
| 1< |
| 17 |
| #108000 |
| 07 |
| #109000 |
| b1 + |
| b1 F |
| b1 ] |
| 1, |
| 1H |
| 17 |
| #110000 |
| 07 |
| #111000 |
| 0A |
| b101111000000000000000000100100 e |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
| #112000 |
| 07 |
| #113000 |
| 0W |
| 1X |
| 1A |
| b101111000000000000000000100100 6 |
| b101111000000000000000000100100 B |
| b101111000000000000000000100100 P |
| 18 |
| 1< |
| 17 |
| #114000 |
| 07 |
| #115000 |
| 1, |
| 1H |
| 17 |
| #116000 |
| 07 |
| #117000 |
| 0A |
| 0< |
| 08 |
| 0, |
| 0H |
| 17 |
