Removed references to "Mega-Project" and replaced them with "User Project".
diff --git a/verilog/rtl/README b/verilog/rtl/README
index 5c05935..bc1d751 100644
--- a/verilog/rtl/README
+++ b/verilog/rtl/README
@@ -43,7 +43,7 @@
mprj_io[4] SCK, housekeeping SPI
mprj_io[5] Rx, UART
mprj_io[6] Tx, UART
- mrpj_io[7] IRQ
+ mprj_io[7] IRQ
The next 4 user GPIO are designed to be used with an SPI flash controller in
the user space. They allow the four pins to be overridden by the housekeeping
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index b5fcff9..b10928c 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -129,7 +129,7 @@
wire gpio_outenb_core;
wire gpio_inenb_core;
- // Mega-Project Control (pad-facing)
+ // User Project Control (pad-facing)
wire mprj_io_loader_resetn;
wire mprj_io_loader_clock;
wire mprj_io_loader_data;
@@ -149,7 +149,7 @@
wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
- // Mega-Project Control (user-facing)
+ // User Project Control (user-facing)
wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
wire [`MPRJ_IO_PADS-1:0] user_io_in;
wire [`MPRJ_IO_PADS-1:0] user_io_out;
@@ -159,7 +159,7 @@
wire mgmt_serial_clock;
wire mgmt_serial_resetn;
- // Mega-Project Control management I/O
+ // User Project Control management I/O
// There are two types of GPIO connections:
// (1) Full Bidirectional: Management connects to in, out, and oeb
// Uses: JTAG and SDO
@@ -278,7 +278,7 @@
wire [127:0] la_output_mprj; // From MPRJ to CPU
wire [127:0] la_oen; // LA output enable from CPU perspective (active-low)
- // WB MI A (Mega Project)
+ // WB MI A (User Project)
wire mprj_cyc_o_core;
wire mprj_stb_o_core;
wire mprj_we_o_core;
@@ -343,7 +343,7 @@
.la_input(la_data_out_mprj),
.la_output(la_output_core),
.la_oen(la_oen),
- // Mega Project IO Control
+ // User Project IO Control
.mprj_io_loader_resetn(mprj_io_loader_resetn),
.mprj_io_loader_clock(mprj_io_loader_clock),
.mprj_io_loader_data(mprj_io_loader_data),
@@ -353,7 +353,7 @@
.sdo_outenb(sdo_outenb),
.jtag_out(jtag_out),
.jtag_outenb(jtag_outenb),
- // Mega Project Slave ports (WB MI A)
+ // User Project Slave ports (WB MI A)
.mprj_cyc_o(mprj_cyc_o_core),
.mprj_stb_o(mprj_stb_o_core),
.mprj_we_o(mprj_we_o_core),
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 9ea31ce..36b08df 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -48,7 +48,7 @@
output flash_io1_di_core,
// porbh, returned to the I/O level shifted down and inverted
input por,
- // Mega-project IOs
+ // User project IOs
inout [`MPRJ_IO_PADS-1:0] mprj_io,
input [`MPRJ_IO_PADS-1:0] mprj_io_out,
input [`MPRJ_IO_PADS-1:0] mprj_io_oeb,
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 45f65a4..0719dc1 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -33,8 +33,8 @@
// Clocking
input clock,
// LA signals
- input [127:0] la_input, // From Mega-Project to cpu
- output [127:0] la_output, // From CPU to Mega-Project
+ input [127:0] la_input, // From User Project to cpu
+ output [127:0] la_output, // From CPU to User Project
output [127:0] la_oen, // LA output enable
// Housekeeping SPI
output sdo_out,
@@ -42,13 +42,13 @@
// JTAG
output jtag_out,
output jtag_outenb,
- // Mega-Project Control Signals
+ // User Project Control Signals
input [MPRJ_IO_PADS-1:0] mgmt_in_data,
output [MPRJ_IO_PADS-1:0] mgmt_out_data,
output mprj_io_loader_resetn,
output mprj_io_loader_clock,
output mprj_io_loader_data,
- // WB MI A (Mega project)
+ // WB MI A (User project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
output mprj_cyc_o,
@@ -173,14 +173,14 @@
.la_input(la_input),
.la_output(la_output),
.la_oen(la_oen),
- // Mega-Project I/O Configuration
+ // User Project I/O Configuration
.mprj_io_loader_resetn(mprj_io_loader_resetn),
.mprj_io_loader_clock(mprj_io_loader_clock),
.mprj_io_loader_data(mprj_io_loader_data),
// I/O data
.mgmt_in_data(mgmt_in_data),
.mgmt_out_data(mgmt_out_data),
- // Mega Project Slave ports (WB MI A)
+ // User Project Slave ports (WB MI A)
.mprj_cyc_o(mprj_cyc_o),
.mprj_stb_o(mprj_stb_o),
.mprj_we_o(mprj_we_o),
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 91dfbd5..6778da0 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -65,16 +65,16 @@
output gpio_inenb_pad, // Connect to inp_dis on gpio pad
// LA signals
- input [127:0] la_input, // From Mega-Project to cpu
- output [127:0] la_output, // From CPU to Mega-Project
+ input [127:0] la_input, // From User Project to cpu
+ output [127:0] la_output, // From CPU to User Project
output [127:0] la_oen, // LA output enable (active low)
- // Mega-Project I/O Configuration (serial load)
+ // User Project I/O Configuration (serial load)
output mprj_io_loader_resetn,
output mprj_io_loader_clock,
output mprj_io_loader_data,
- // Mega-Project pad data (when management SoC controls the pad)
+ // User Project pad data (when management SoC controls the pad)
input [MPRJ_IO_PADS-1:0] mgmt_in_data,
output [MPRJ_IO_PADS-1:0] mgmt_out_data,
@@ -121,7 +121,7 @@
// SPI master->slave direct link
output hk_connect,
- // WB MI A (Mega project)
+ // WB MI A (User project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
output mprj_cyc_o,
@@ -636,7 +636,7 @@
.la_oen(la_oen)
);
- // WB Slave Mega-Project Control
+ // WB Slave User Project Control
wire mprj_ctrl_stb_i;
wire mprj_ctrl_ack_o;
wire [31:0] mprj_ctrl_dat_o;
