Merge pull request #32 from dan-rodrigues/user_proj_wb_ack
user_proj_example.v: Fix wbs_ack_o wiring
diff --git a/openlane/DFFRAM/config.tcl b/openlane/DFFRAM/config.tcl
index 7782cee..3e3f4d2 100644
--- a/openlane/DFFRAM/config.tcl
+++ b/openlane/DFFRAM/config.tcl
@@ -3,7 +3,7 @@
set ::env(DESIGN_NAME) DFFRAM
# Change if needed
-set ::env(VERILOG_FILES) $script_dir/../../verilog/gl/DFFRAM.gl.v
+set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/DFFRAM.v
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
# Fill this
@@ -14,7 +14,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 630 630"
+set ::env(DIE_AREA) "0 0 750 525"
set ::env(PDN_CFG) $script_dir/pdn.tcl
diff --git a/verilog/gl/DFFRAM.gl.v b/verilog/rtl/DFFRAM.v
similarity index 99%
rename from verilog/gl/DFFRAM.gl.v
rename to verilog/rtl/DFFRAM.v
index 34db22d..176a549 100644
--- a/verilog/gl/DFFRAM.gl.v
+++ b/verilog/rtl/DFFRAM.v
@@ -1,5 +1,30 @@
/* Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 12.0.0 -fPIC -Os) */
+`ifndef USE_CUSTOM_DFFRAM
+
+module DFFRAM(CLK, WE, EN, Di, Do, A);
+ input CLK;
+ input [3:0] WE;
+ input EN;
+ input [31:0] Di;
+ output reg [31:0] Do;
+ input [7:0] A;
+
+reg [31:0] mem [0:`MEM_WORDS-1];
+
+always @(posedge CLK) begin
+ if (EN == 1'b1) begin
+ Do <= mem[A];
+ if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0];
+ if (WE[1]) mem[A][15: 8] <= Di[15: 8];
+ if (WE[2]) mem[A][23:16] <= Di[23:16];
+ if (WE[3]) mem[A][31:24] <= Di[31:24];
+ end
+end
+endmodule
+
+
+`else
module DFFRAM(CLK, WE, EN, Di, Do, A);
input [7:0] A;
wire \B_0_0.CLK ;
@@ -112769,3 +112794,4 @@
.X(\B_0_0.WE[3] )
);
endmodule
+`endif // USE_CUSTOM_DFFRAM
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index d7c123f..23fb906 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -42,6 +42,7 @@
`include "clock_div.v"
`include "simple_por.v"
`include "storage_bridge_wb.v"
+`include "DFFRAM.v"
`include "sram_1rw1r_32_256_8_sky130.v"
`include "storage.v"
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 8c96402..f5a6c90 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -7,8 +7,10 @@
// Type and size of soc_mem
// `define USE_OPENRAM
+// `define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
`define MEM_WORDS 256
// Number of RAM blocks for the mgmt_core
`define MGMT_BLOCKS 2
-`define USER_BLOCKS 6
\ No newline at end of file
+`define USER_BLOCKS 6
