Add a global defines.v and rely less on parameters
- This is mainly to avoid "accidents" with default parameter values
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 675a873..4aba1fe 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -12,13 +12,10 @@
`timescale 1 ns / 1 ps
-`define USE_OPENRAM
`define USE_POWER_PINS
`define UNIT_DELAY #1
-`define MPRJ_IO_PADS 38
-`define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */
-
+`include "defines.v"
`include "pads.v"
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
@@ -316,10 +313,7 @@
wire mprj_vdd_pwrgood;
wire mprj2_vdd_pwrgood;
- mgmt_core #(
- .MPRJ_IO_PADS(`MPRJ_IO_PADS),
- .MPRJ_PWR_PADS(`MPRJ_PWR_PADS)
- ) soc (
+ mgmt_core soc (
`ifdef LVS
.vdd(vccd),
.vss(vssa),
@@ -434,10 +428,7 @@
/* Wrapper module around the user project */
/*----------------------------------------------*/
- user_project_wrapper #(
- .IO_PADS(`MPRJ_IO_PADS),
- .PWR_PADS(`MPRJ_PWR_PADS)
- ) mprj (
+ user_project_wrapper mprj (
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
.vssa1(vssa1), // User area 1 analog ground
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
new file mode 100644
index 0000000..5cc6d03
--- /dev/null
+++ b/verilog/rtl/defines.v
@@ -0,0 +1,11 @@
+// Global parameters
+
+`define MPRJ_IO_PADS 38
+`define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */
+
+// Size of soc_mem_synth
+`define MEM_SYNTH_WORDS 1024
+
+// Type and size of soc_mem
+`define USE_OPENRAM
+`define MEM_WORDS 256
diff --git a/verilog/rtl/mem_synth_wb.v b/verilog/rtl/mem_synth_wb.v
index d54ddf6..c4a1cc4 100644
--- a/verilog/rtl/mem_synth_wb.v
+++ b/verilog/rtl/mem_synth_wb.v
@@ -1,6 +1,4 @@
-module mem_synth_wb #(
- parameter integer MEM_WORDS = 1024
-)(
+module mem_synth_wb (
input wb_clk_i,
input wb_rst_i,
@@ -37,9 +35,7 @@
end
end
- soc_mem_synth # (
- .MEM_WORDS(MEM_WORDS)
- ) mem (
+ soc_mem_synth mem (
.clk(wb_clk_i),
.ena(valid),
.wen(wen),
@@ -50,9 +46,7 @@
endmodule
-module soc_mem_synth #(
- parameter integer MEM_WORDS = 2048
-)(
+module soc_mem_synth (
input clk,
input ena,
input [3:0] wen,
@@ -62,7 +56,7 @@
);
reg [31:0] rdata;
- reg [31:0] mem [0:MEM_WORDS-1];
+ reg [31:0] mem [0:`MEM_SYNTH_WORDS-1];
always @(posedge clk) begin
if (ena == 1'b1) begin
@@ -74,4 +68,4 @@
end
end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 882f1c7..f9cfd62 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -1,6 +1,4 @@
-module mem_wb # (
- parameter integer MEM_WORDS = 256
-) (
+module mem_wb (
input wb_clk_i,
input wb_rst_i,
@@ -50,7 +48,11 @@
`endif
- soc_mem mem(
+ soc_mem
+`ifndef USE_OPENRAM
+ #(.WORDS(`MEM_WORDS))
+`endif
+ mem (
.clk(wb_clk_i),
.ena(valid),
.wen(wen),
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 38a4238..863bd98 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,7 +1,4 @@
-module mgmt_core #(
- parameter MPRJ_IO_PADS = 32,
- parameter MPRJ_PWR_PADS = 32
-) (
+module mgmt_core (
`ifdef LVS
inout vdd1v8,
inout vss,
@@ -43,9 +40,9 @@
output jtag_out,
output jtag_outenb,
// User Project Control Signals
- input [MPRJ_IO_PADS-1:0] mgmt_in_data,
- output [MPRJ_IO_PADS-1:0] mgmt_out_data,
- output [MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
+ input [`MPRJ_IO_PADS-1:0] mgmt_in_data,
+ output [`MPRJ_IO_PADS-1:0] mgmt_out_data,
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
input mprj_vcc_pwrgood,
input mprj2_vcc_pwrgood,
input mprj_vdd_pwrgood,
@@ -139,11 +136,7 @@
// the pad. All others have OEB controlled by the configuration bit
// in the control block.
- mgmt_soc #(
- .MPRJ_IO_PADS(MPRJ_IO_PADS),
- .MPRJ_PWR_PADS(MPRJ_PWR_PADS)
- ) soc (
-
+ mgmt_soc soc (
`ifdef LVS
.vdd1v8(vdd1v8),
.vss(vss),
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 478b9ee..55d0d2d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -44,10 +44,7 @@
`include "convert_gpio_sigs.v"
`include "mem_synth_wb.v"
-module mgmt_soc #(
- parameter MPRJ_IO_PADS = 32,
- parameter MPRJ_PWR_PADS = 32
-) (
+module mgmt_soc (
`ifdef LVS
inout vdd1v8, /* 1.8V domain */
inout vss,
@@ -81,9 +78,9 @@
output mprj_io_loader_data,
// User Project pad data (when management SoC controls the pad)
- input [MPRJ_IO_PADS-1:0] mgmt_in_data,
- output [MPRJ_IO_PADS-1:0] mgmt_out_data,
- output [MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
+ input [`MPRJ_IO_PADS-1:0] mgmt_in_data,
+ output [`MPRJ_IO_PADS-1:0] mgmt_out_data,
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
// IRQ
input irq_spi, // IRQ from standalone SPI
@@ -144,9 +141,7 @@
output [31:0] mprj_dat_o
);
/* Memory reverted back to 256 words while memory has to be synthesized */
- parameter integer MEM_WORDS = 256;
- parameter integer MEM_SYNTH_WORDS = 1024;
- parameter [31:0] STACKADDR = (4*(MEM_WORDS + MEM_SYNTH_WORDS)); // end of memory
+ parameter [31:0] STACKADDR = (4*(`MEM_WORDS + `MEM_SYNTH_WORDS)); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 1000_0000;
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
@@ -660,13 +655,13 @@
wire mprj_ctrl_stb_i;
wire mprj_ctrl_ack_o;
wire [31:0] mprj_ctrl_dat_o;
- wire [MPRJ_IO_PADS-1:0] mgmt_out_pre;
+ wire [`MPRJ_IO_PADS-1:0] mgmt_out_pre;
// Bits assigned to specific functions as outputs prevent the
// mprj GPIO-as-output from applying data when that function
// is active
- assign mgmt_out_data[MPRJ_IO_PADS-1:16] = mgmt_out_pre[MPRJ_IO_PADS-1:16];
+ assign mgmt_out_data[`MPRJ_IO_PADS-1:16] = mgmt_out_pre[`MPRJ_IO_PADS-1:16];
// Routing of output monitors (PLL, trap, clk1, clk2)
assign mgmt_out_data[15] = clk2_output_dest ? user_clk : mgmt_out_pre[15];
@@ -678,9 +673,7 @@
assign mgmt_out_data[5:0] = mgmt_out_pre[5:0];
mprj_ctrl_wb #(
- .BASE_ADR(MPRJ_CTRL_ADR),
- .IO_PADS(MPRJ_IO_PADS),
- .PWR_PADS(MPRJ_PWR_PADS)
+ .BASE_ADR(MPRJ_CTRL_ADR)
) mprj_ctrl (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -709,9 +702,7 @@
wire mem_ack_o;
wire [31:0] mem_dat_o;
- mem_wb #(
- .MEM_WORDS(MEM_WORDS)
- ) soc_mem (
+ mem_wb soc_mem (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -731,9 +722,7 @@
wire mem_synth_ack_o;
wire [31:0] mem_synth_dat_o;
- mem_synth_wb #(
- .MEM_WORDS(MEM_SYNTH_WORDS)
- ) soc_mem_synth (
+ mem_synth_wb soc_mem_synth (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(cpu_adr_o),
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 961b29a..0f385de 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -3,9 +3,7 @@
parameter XFER = 8'h 00,
parameter PWRDATA = 8'h 04,
parameter IODATA = 8'h 08, // One word per 32 IOs
- parameter IOCONFIG = 8'h 20,
- parameter IO_PADS = 32, // Number of IO control registers (may be > 32)
- parameter PWR_PADS = 32 // Number of power control registers (always < 32)
+ parameter IOCONFIG = 8'h 20
)(
input wb_clk_i,
input wb_rst_i,
@@ -31,11 +29,11 @@
output jtag_oenb_state,
// Read/write data to each GPIO pad from management SoC
- input [IO_PADS-1:0] mgmt_gpio_in,
- output [IO_PADS-1:0] mgmt_gpio_out,
+ input [`MPRJ_IO_PADS-1:0] mgmt_gpio_in,
+ output [`MPRJ_IO_PADS-1:0] mgmt_gpio_out,
// Write data to power controls
- output [PWR_PADS-1:0] pwr_ctrl_out
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out
);
wire resetn;
wire valid;
@@ -53,9 +51,7 @@
.XFER(XFER),
.PWRDATA(PWRDATA),
.IODATA(IODATA),
- .IOCONFIG(IOCONFIG),
- .IO_PADS(IO_PADS),
- .PWR_PADS(PWR_PADS)
+ .IOCONFIG(IOCONFIG)
) mprj_ctrl (
.clk(wb_clk_i),
.resetn(resetn),
@@ -84,8 +80,6 @@
parameter PWRDATA = 8'h 04,
parameter IODATA = 8'h 08,
parameter IOCONFIG = 8'h 20,
- parameter IO_PADS = 32,
- parameter PWR_PADS = 32,
parameter IO_CTRL_BITS = 13
)(
input clk,
@@ -103,8 +97,8 @@
output serial_data_out,
output sdo_oenb_state,
output jtag_oenb_state,
- input [IO_PADS-1:0] mgmt_gpio_in,
- output [IO_PADS-1:0] mgmt_gpio_out
+ input [`MPRJ_IO_PADS-1:0] mgmt_gpio_in,
+ output [`MPRJ_IO_PADS-1:0] mgmt_gpio_out
);
`define IDLE 2'b00
@@ -112,26 +106,26 @@
`define XBYTE 2'b10
`define LOAD 2'b11
- localparam IO_WORDS = (IO_PADS % 32 != 0) + (IO_PADS / 32);
+ localparam IO_WORDS = (`MPRJ_IO_PADS % 32 != 0) + (`MPRJ_IO_PADS / 32);
localparam IO_BASE_ADR = (BASE_ADR | IOCONFIG);
localparam OEB = 1; // Offset of output enable in shift register.
localparam INP_DIS = 3; // Offset of input disable in shift register.
- reg [IO_CTRL_BITS-1:0] io_ctrl[IO_PADS-1:0]; // I/O control, 1 word per gpio pad
- reg [IO_PADS-1:0] mgmt_gpio_outr; // I/O write data, 1 bit per gpio pad
- wire [IO_PADS-1:0] mgmt_gpio_out; // I/O write data output when input disabled
- reg [PWR_PADS-1:0] pwr_ctrl_out; // Power write data, 1 bit per power pad
+ reg [IO_CTRL_BITS-1:0] io_ctrl[`MPRJ_IO_PADS-1:0]; // I/O control, 1 word per gpio pad
+ reg [`MPRJ_IO_PADS-1:0] mgmt_gpio_outr; // I/O write data, 1 bit per gpio pad
+ wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_out; // I/O write data output when input disabled
+ reg [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out; // Power write data, 1 bit per power pad
reg xfer_ctrl; // Transfer control (1 bit)
wire [IO_WORDS-1:0] io_data_sel; // wishbone selects
wire pwr_data_sel;
wire xfer_sel;
- wire [IO_PADS-1:0] io_ctrl_sel;
+ wire [`MPRJ_IO_PADS-1:0] io_ctrl_sel;
wire [31:0] iomem_rdata_pre;
- wire [IO_PADS-1:0] mgmt_gpio_in;
+ wire [`MPRJ_IO_PADS-1:0] mgmt_gpio_in;
wire sdo_oenb_state, jtag_oenb_state;
@@ -143,7 +137,7 @@
assign jtag_oenb_state = io_ctrl[0][OEB];
assign sdo_oenb_state = io_ctrl[1][OEB];
- `define wtop (((i+1)*32 > IO_PADS) ? IO_PADS-1 : (i+1)*32-1)
+ `define wtop (((i+1)*32 > `MPRJ_IO_PADS) ? `MPRJ_IO_PADS-1 : (i+1)*32-1)
`define wbot (i*32)
`define rtop (`wtop - `wbot)
@@ -159,7 +153,7 @@
assign io_data_sel[i] = (iomem_addr[7:0] == (IODATA + i*4));
end
- for (i=0; i<IO_PADS; i=i+1) begin
+ for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
assign io_ctrl_sel[i] = (iomem_addr[7:0] == (IO_BASE_ADR[7:0] + i*4));
assign mgmt_gpio_out[i] = (io_ctrl[i][INP_DIS] == 1'b1) ?
mgmt_gpio_outr[i] : 1'bz;
@@ -180,7 +174,7 @@
assign iomem_rdata_pre = (io_data_sel[i]) ? mgmt_gpio_in[`wtop:`wbot] : 'bz;
end
- for (i=0; i<IO_PADS; i=i+1) begin
+ for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
assign iomem_rdata_pre = (io_ctrl_sel[i]) ? io_ctrl[i] : 'bz;
end
endgenerate
@@ -215,7 +209,7 @@
if (xfer_sel) begin
if (iomem_wstrb[0]) xfer_ctrl <= iomem_wdata[0];
end else if (pwr_data_sel) begin
- if (iomem_wstrb[0]) pwr_ctrl_out <= iomem_wdata[PWR_PADS-1:0];
+ if (iomem_wstrb[0]) pwr_ctrl_out <= iomem_wdata[`MPRJ_PWR_PADS-1:0];
end
end else begin
xfer_ctrl <= 1'b0; // Immediately self-resetting
@@ -244,7 +238,7 @@
end
end
- for (i=0; i<IO_PADS; i=i+1) begin
+ for (i=0; i<`MPRJ_IO_PADS; i=i+1) begin
always @(posedge clk) begin
if (!resetn) begin
// NOTE: This initialization must match the defaults passed
@@ -288,14 +282,14 @@
xfer_state <= `IDLE;
xfer_count <= 4'd0;
- pad_count <= IO_PADS;
+ pad_count <= `MPRJ_IO_PADS;
serial_resetn <= 1'b0;
serial_clock <= 1'b0;
end else begin
if (xfer_state == `IDLE) begin
- pad_count <= IO_PADS;
+ pad_count <= `MPRJ_IO_PADS;
serial_resetn <= 1'b1;
serial_clock <= 1'b0;
if (xfer_ctrl == 1'b1) begin
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index d010e77..a72d99e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -20,8 +20,6 @@
*/
module user_proj_example #(
- parameter IO_PADS = 38,
- parameter PWR_PADS = 4,
parameter BITS = 32
)(
inout vdda1, // User area 1 3.3V supply
@@ -51,16 +49,16 @@
input [127:0] la_oen,
// IOs
- input [IO_PADS-1:0] io_in,
- output [IO_PADS-1:0] io_out,
- output [IO_PADS-1:0] io_oeb
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb
);
wire clk;
wire rst;
- wire [IO_PADS-1:0] io_in;
- wire [IO_PADS-1:0] io_out;
- wire [IO_PADS-1:0] io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
wire [31:0] rdata;
wire [31:0] wdata;
@@ -78,7 +76,7 @@
// IO
assign io_out = count;
- assign io_oeb = {(IO_PADS-1){rst}};
+ assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index b37d2e5..488e4cc 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -14,8 +14,6 @@
*/
module user_project_wrapper #(
- parameter IO_PADS = 38,
- parameter PWR_PADS = 4,
parameter BITS = 32
)(
inout vdda1, // User area 1 3.3V supply
@@ -45,9 +43,9 @@
input [127:0] la_oen,
// IOs
- input [IO_PADS-1:0] io_in,
- output [IO_PADS-1:0] io_out,
- output [IO_PADS-1:0] io_oeb,
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
// Independent clock (on independent integer divider)
input user_clock2
@@ -57,10 +55,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
- user_proj_example #(
- .IO_PADS(IO_PADS),
- .PWR_PADS(PWR_PADS)
- ) mprj (
+ user_proj_example mprj (
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
.vssa1(vssa1), // User area 1 analog ground
@@ -75,7 +70,7 @@
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
- // MGMT SoC Wishbone Slave
+ // MGMT SoC Wishbone Slave
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
