Seperated mgmt and user storage blocks base addresses
diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
index ccfdf95..4d86f29 100644
--- a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -1,17 +1,20 @@
`define MGMT_BLOCKS 2
`define USER_BLOCKS 4
+`define MGMT_BASE_ADR 32'h 0100_0000
+`define USER_BASE_ADR 32'h 0200_0000
-`define BASE_ADR { \
- {8'h07, {24{1'b0}} }, \
- {8'h06, {24{1'b0}} }, \
- {8'h05, {24{1'b0}} }, \
- {8'h04, {24{1'b0}} }, \
- {8'h03, {24{1'b0}} }, \
- {8'h02, {24{1'b0}} }, \
- {8'h01, {24{1'b0}} } \
+`define MGMT_BLOCKS_ADR { \
+ {24'h 10_0000}, \
+ {24'h 00_0000} \
}\
+`define USER_BLOCKS_ADR { \
+ {24'h 00_0000}, \
+ {24'h 10_0000}, \
+ {24'h 20_0000}, \
+ {24'h 30_0000} \
+}\
// `define DBG
`include "sram_1rw1r_32_256_8_sky130.v"
@@ -95,7 +98,10 @@
end
reg [31:0] ref_data [255: 0];
- reg [32*(`MGMT_BLOCKS+`USER_BLOCKS)-1:0] base_adr = `BASE_ADR;
+ reg [24*(`MGMT_BLOCKS)-1:0] mgmt_blocks_adr = `MGMT_BLOCKS_ADR;
+ reg [24*(`USER_BLOCKS)-1:0] user_blocks_adr = `USER_BLOCKS_ADR;
+
+
reg [31:0] block_adr;
integer i,j;
@@ -112,7 +118,7 @@
if (i == 0) begin
ref_data[j] = $urandom_range(0, 2**30);
end
- block_adr = base_adr[32*i+:32] + j;
+ block_adr = mgmt_blocks_adr[24*i+:24] + j | `MGMT_BASE_ADR;
mgmt_write(block_adr, ref_data[j]);
#2;
end
@@ -120,7 +126,7 @@
for (i = 0; i< `MGMT_BLOCKS; i = i +1) begin
for ( j = 0; j < 100; j = j + 1) begin
- block_adr = base_adr[32*i+:32] + j;
+ block_adr = mgmt_blocks_adr[24*i+:24] + j | `MGMT_BASE_ADR;
mgmt_read(block_adr, 0);
if (wb_mgmt_dat_o !== ref_data[j]) begin
$display("Monitor: MGMT R/W Operation Failed");
@@ -155,7 +161,7 @@
$finish;
end
- block_adr = base_adr[32*(i+`MGMT_BLOCKS)+:32] + j;
+ block_adr = user_blocks_adr[24*i+:24] + j | `USER_BASE_ADR;
mgmt_read(block_adr,1);
if(wb_user_dat_o !== ref_data[j])begin
$display("Monitor: MGMT RO Operation Failed");
@@ -264,7 +270,10 @@
storage_bridge_wb #(
.USER_BLOCKS(`USER_BLOCKS),
.MGMT_BLOCKS(`MGMT_BLOCKS),
- .BASE_ADDR(`BASE_ADR)
+ .MGMT_BASE_ADR(`MGMT_BASE_ADR),
+ .USER_BASE_ADR(`USER_BASE_ADR),
+ .MGMT_BLOCKS_ADR(`MGMT_BLOCKS_ADR),
+ .USER_BLOCKS_ADR(`USER_BLOCKS_ADR)
) wb_bridge (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index 1c89ca5..b8bf2c8 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -1,8 +1,10 @@
module storage_bridge_wb #(
parameter USER_BLOCKS = 4,
- parameter MGMT_BLOCKS = 2
+ parameter MGMT_BLOCKS = 2,
+ parameter MGMT_BASE_ADR = 32'h 0100_0000,
+ parameter USER_BASE_ADR = 32'h 0200_0000
) (
- // MGMT_AREA R/W WB Interface (#of WB Slaves = MGMT_BLOCKS )
+ // MGMT_AREA R/W WB Interface
input wb_clk_i,
input wb_rst_i,
@@ -15,7 +17,7 @@
output reg [1:0] wb_ack_o,
output reg [31:0] wb_mgmt_dat_o,
- // MGMT_AREA RO WB Interface (USER_BLOCKS)
+ // MGMT_AREA RO WB Interface
output reg [31:0] wb_user_dat_o,
// MGMT Area native memory interface
@@ -26,25 +28,25 @@
output [31:0] mgmt_wdata,
input [(MGMT_BLOCKS*32)-1:0] mgmt_rdata,
- // MGMT_AREA RO Interface (USER_BLOCKS)
+ // MGMT_AREA RO Interface
output [USER_BLOCKS-1:0] mgmt_user_ena,
output [7:0] mgmt_user_addr,
input [(USER_BLOCKS*32)-1:0] mgmt_user_rdata
);
- localparam RAM_BLOCKS = USER_BLOCKS + MGMT_BLOCKS;
- parameter [(RAM_BLOCKS*32)-1:0] BASE_ADDR = {
- // User partition
- {32'h 0700_0000},
- {32'h 0600_0000},
- {32'h 0500_0000},
- {32'h 0400_0000},
- {32'h 0300_0000},
- // MGMT partition
- {32'h 0200_0000},
- {32'h 0100_0000}
+ parameter [(MGMT_BLOCKS*24)-1:0] MGMT_BLOCKS_ADR = {
+ {24'h 10_0000},
+ {24'h 00_0000}
};
- parameter ADR_MASK = 32'h FF00_0000;
+
+ parameter [(USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
+ {24'h 30_0000},
+ {24'h 20_0000},
+ {24'h 10_0000},
+ {24'h 00_0000}
+ };
+
+ parameter ADR_MASK = 24'h FF_0000;
wire [1:0] valid;
wire [1:0] wen;
@@ -68,24 +70,30 @@
end
// Address decoding
- wire [RAM_BLOCKS-1: 0] ram_sel;
+ wire [MGMT_BLOCKS-1: 0] mgmt_sel;
+ wire [USER_BLOCKS-1: 0] user_sel;
+
+ wire [23:0] test = (wb_adr_i[23:0] & ADR_MASK);
+ wire iste = test == MGMT_BLOCKS_ADR[23:0];
genvar iS;
generate
- for (iS = 0; iS < RAM_BLOCKS; iS = iS + 1) begin
- assign ram_sel[iS] =
- ((wb_adr_i & ADR_MASK) == BASE_ADDR[(iS+1)*32-1:iS*32]);
+ for (iS = 0; iS < MGMT_BLOCKS; iS = iS + 1) begin
+ assign mgmt_sel[iS] =
+ ((wb_adr_i[23:0] & ADR_MASK) == MGMT_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
+ end
+ for (iS = 0; iS < USER_BLOCKS; iS = iS + 1) begin
+ assign user_sel[iS] =
+ ((wb_adr_i[23:0] & ADR_MASK) == USER_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
end
endgenerate
// Management SoC interface
- assign mgmt_ena = valid[0] ? ~ram_sel[1:0] : {MGMT_BLOCKS{1'b1}};
+ assign mgmt_ena = valid[0] ? ~mgmt_sel : {MGMT_BLOCKS{1'b1}};
assign mgmt_wen = ~{MGMT_BLOCKS{wen[0]}};
assign mgmt_wen_mask = {MGMT_BLOCKS{wen_mask[3:0]}};
assign mgmt_addr = wb_adr_i[7:0];
assign mgmt_wdata = wb_dat_i[31:0];
- wire [1:0] mgmt_sel = ram_sel[1:0];
-
integer i;
always @(*) begin
wb_mgmt_dat_o = {32{1'b0}};
@@ -94,11 +102,9 @@
end
// User Interface
- assign mgmt_user_ena = valid[1] ? ~ram_sel[5:2] : {USER_BLOCKS{1'b1}};
+ assign mgmt_user_ena = valid[1] ? ~user_sel : {USER_BLOCKS{1'b1}};
assign mgmt_user_addr = wb_adr_i[7:0];
- wire [3:0] user_sel = ram_sel [5:2];
-
integer j;
always @(*) begin
wb_user_dat_o = {32{1'b0}};
