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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-015 / 0b6219d234cc044a8fb7ed7b544b26631d207577
commit0b6219d234cc044a8fb7ed7b544b26631d207577[log] [tgz]
authorAhmed Ghazy <ax3ghazy@aucegypt.edu>Mon Oct 26 15:43:57 2020 +0200
committerAhmed Ghazy <ax3ghazy@aucegypt.edu>Wed Oct 28 22:58:29 2020 +0200
treee11c193bdd343f97a34ce0e81fe11c92d055f842
parent496a08abbe49b76515a0f8f460467969beeb09e3 [diff]
Fix to an issue with index arithmetic

- Only use an additional {IO,PWR}_WORD when having non-multiples of 32
  pads
- rtop corrected to be an index rather than a count
1 file changed
tree: e11c193bdd343f97a34ce0e81fe11c92d055f842
  1. def/
  2. doc/
  3. gds/
  4. lef/
  5. mag/
  6. openlane/
  7. verilog/
  8. LICENSE
  9. README.md
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.