- df4dd88 Minor RTL fixes, switching to wrapped GPIOV2 by Ahmed Ghazy · 4 years, 4 months ago
- 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
- 08cd6eb add default nettype none by Matt Venn · 4 years, 4 months ago
- b9a8c91 user_proj_example: fix wbs_ack_o wiring by Dan Rodrigues · 4 years, 4 months ago
- 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
- b6dd152 Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
- 21a9aac Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 5 months ago
- ef2b68d Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 5 months ago
- 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 5 months ago
- 0553751 Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago[Renamed (75%) from verilog/rtl/mprj_counter.v]
- 0d14e6e harness phase1 initial commit by shalan · 4 years, 7 months ago
