Added ngspice netlist and testbenches for the power-on-reset circuit.
diff --git a/ngspice/current_test.spice b/ngspice/current_test.spice new file mode 100644 index 0000000..606eb2d --- /dev/null +++ b/ngspice/current_test.spice
@@ -0,0 +1,70 @@ +*------------------------------------------------------------------- +* Simple POR circuit for Caravel current mirror test +*------------------------------------------------------------------- + +.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt + +* Note: 20 resistors of length 25um connected in series +Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500 +Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149 + +* voltage sources at 0V for measuring current in each branch + +Vm1 vssm1 vss DC=0 +Vm2 vdda vddm2 DC=0 +Vm3 vdda vddm3 DC=0 +Vm4 vssm4 vss DC=0 +Vm5 vssm5 vss DC=0 +Vm6 vdda vddm6 DC=0 +Vm7 vdda vddm7 DC=0 + +* D G S B +Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8 +Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 + +* Check branch currents in each mirror branch. +* 1st branch should be 240nA +* 2nd branch should be 30nA +* 3rd branch should be 4.3nA +* 4th branch should be 612pA +* +* Result: vin sits at 0.7590 (close to 0.7575 target) +* I(Vm1/2) = 202.80 nA +* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77 +* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70 +* I(Vm7) = 0.67 pA (should be /7) actually /6.80 + +*---------------------------- +* Testbench circuit +*---------------------------- +Vpwr vdda vss DC=3.3 +Rgnd vss 0 0.01 +Rload vcap vss 1MEG +*---------------------------- + +*---------------------------- +* Testbench control +*---------------------------- +.control +op +print V(vin) +print I(Vm1) +print I(Vm2) +print I(Vm3) +print I(Vm4) +print I(Vm5) +print I(Vm6) +print I(Vm7) +.endc + +.end +
diff --git a/ngspice/simple_por.spice b/ngspice/simple_por.spice new file mode 100644 index 0000000..e4fd85e --- /dev/null +++ b/ngspice/simple_por.spice
@@ -0,0 +1,67 @@ +*------------------------------------------------------------------- +* Simple POR circuit for Caravel +*------------------------------------------------------------------- +* +* Architecture: +* +* Resistive divider sets mvnfet transistor gate voltage to ??V +* mvnfet current is 240nA nominal +* mvnfet drives current mirror at 1/400x to 600pA through mvpfet +* current feeds 1.84pF capacitor (double MiM at 30um x 30um) +* voltage across capacitor is input to chain of two schmitt trigger +* inverters. +* +* Q = C * V = I * dt +* +* t = C * V / I = 1.84pF * 3.3V / 600pA = 10ms +* +* ~400x step-down done by mirroring 1:8, 1:7, 1:7 (= 392) +* +* From DC sweep test result, V = 0.7575 on the transtor gate at vin +* Resistor divider at fraction 0.23. +* This yields resistor lengths of 500 on top, 149 on the bottom +* +* Actual response of this circuit by ngspice simulation is 15ms. +*------------------------------------------------------------------- + +.subckt simple_por vdda vccd vss por_h por_l porb_l + +Xcap1 vcap vss sky130_fd_pr__cap_mim_m3_1 l=30 w=30 +Xcap2 vcap vss sky130_fd_pr__cap_mim_m3_2 l=30 w=30 + +* Note: 20 resistors of length 25um connected in series +Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500 +Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149 + +* Triple current mirror, ratios 8:1, 7:1, and 7:1, with p-cascodes +* D G S B +Xm1 casc1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm2 mir1 mir1 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8 +Xm3 mir2 mir1 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm4 casc2 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm5 casc3 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm6 mir3 mir3 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm7 mir4 mir3 vdda vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 + +* Buffered with schmitt trigger buffer +Xtrig vcap vss vss vdda vdda out sky130_fd_sc_hvl__schmittbuf_1 + +* High voltage output (buffer) +Xbuf out vss vss vdda vdda por_h sky130_fd_sc_hvl__buf_8 + +* Level shift down (buffer) +Xlv1 out vss vss vccd vccd por_l sky130_fd_sc_hvl__buf_8 + +* Level shift down (inverter) +Xlv2 out vss vss vccd vccd porb_l sky130_fd_sc_hvl__inv_8 + +* No tap cell in library? +* Xtap vdda vss sky130_fd_sc_hvl__tapvpwrvgnd_1 + +.ends + +.end
diff --git a/ngspice/simple_por_tb.spice b/ngspice/simple_por_tb.spice new file mode 100644 index 0000000..815f4fa --- /dev/null +++ b/ngspice/simple_por_tb.spice
@@ -0,0 +1,36 @@ +*------------------------------------------------------------------- +* Simple POR circuit for Caravel +*------------------------------------------------------------------- +* +* Architecture: see simple_por.spice +* Response of this circuit by ngspice simulation is a ~15ms delay. +*------------------------------------------------------------------- + +.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt +.include /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice +.include simple_por.spice + +*---------------------------- +* Testbench circuit +*---------------------------- +Vpwr vdda vss DC=0 PWL(0.0 0 100u 0 5m 3.3) +Vdig vccd vss DC=0 PWL(0.0 0 300u 0 5.3m 1.8) +Rgnd vss 0 0.01 +Cload1 por_h vss 1E-12 +Cload2 por_l vss 1E-12 +Cload3 porb_l vss 1E-12 +Xpor vdda vccd vss por_h por_l porb_l simple_por +*---------------------------- + +*---------------------------- +* Testbench control +*---------------------------- +.control +tran 10u 20m +plot por_h +plot por_l +plot porb_l +.endc + +.end +
diff --git a/ngspice/threshold_test_tb.spice b/ngspice/threshold_test_tb.spice new file mode 100644 index 0000000..f7befa1 --- /dev/null +++ b/ngspice/threshold_test_tb.spice
@@ -0,0 +1,32 @@ +*------------------------------------------------------------------- +* Threshold test for POR circuit +* Determine gate voltage at which the HV NFET draws 240nA nominal +* +* Result: 0.7575V +*------------------------------------------------------------------- + +.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt + + +*---------------------------- +* Testbench circuit +*---------------------------- +Rtest vdda mir1 1MEG +Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 + +Vgate vin vss DC=0 +Vpwr vdda vss DC=3.3 +Rgnd vss 0 0.1 + +*---------------------------- +* Testbench control +*---------------------------- +.control +* DC sweep from 0.7 to 0.8V +dc Vgate 0.7 0.8 0.001 +wrdata test.data Vpwr#branch vin + +.endc + +.end +
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v index 6307e79..f04fa5c 100644 --- a/verilog/rtl/simple_por.v +++ b/verilog/rtl/simple_por.v
@@ -22,7 +22,8 @@ end // Emulate current source on capacitor as a 500ns delay either up or - // down. + // down. Note that this is sped way up for verilog simulation; the + // actual circuit is set to a 15ms delay. always @(posedge vdd3v3) begin #500 inode <= 1'b1;