| commit | f925edfa7a67b4c55aabc1e28a10bc4a4f6a4b4c | [log] [tgz] |
|---|---|---|
| author | agorararmard <aagouhar@efabless.com> | Thu Nov 26 20:00:29 2020 +0200 |
| committer | agorararmard <aagouhar@efabless.com> | Thu Nov 26 20:00:29 2020 +0200 |
| tree | f6564cc797e09aa537b7795ce8813d7cbdfb9acf | |
| parent | b3eca4c5586eb5aebdf3b2e8182522d044df049f [diff] |
[Docs]: WIP how to run documentation -- rev. 1
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
Start by cloning the repo and uncompressing the files.
git clone https://github.com/efabless/caravel.git cd caravel make uncompress
Then, you can learn more about the caravel chip by watching these video:
Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper.
If you will use OpenLANE to harden your design, go through the instructions in this README.md.
Then, you will need to put your design aboard the Caravel chip. In the Caravel directory, make sure you have the following:
./gds/ directory.Run the following command:
export PDK_ROOT=<The place where the installed pdk resides> make
This should merge the GDSes using magic and you'll end up with your version of ./gds/caravel.gds.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample user project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: