commit f328311ca3feab79919b3a57c4bb6b5aba2b23ae
author Dan Rodrigues <danrr.gh.oss@gmail.com> Sun Nov 08 13:15:21 2020 +1100
committer Dan Rodrigues <danrr.gh.oss@gmail.com> Sun Nov 08 13:15:21 2020 +1100
tree 010087c65a898f714aaeea2997717c0116ba8e8f
parent 6498e97a0ba36682fd57f0d73ba9a70756c8922f

user_proj_example: fix wbs_ack_o wiring

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index a72d99e..f1feed5 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -91,7 +91,7 @@
     ) counter(
         .clk(clk),
         .reset(rst),
-        .ready(wbs_ack_i),
+        .ready(wbs_ack_o),
         .valid(valid),
         .rdata(rdata),
         .wdata(wbs_dat_i),