Updated openlane configs for mgmt_core and digital_pll
diff --git a/openlane/digital_pll/config.tcl b/openlane/digital_pll/config.tcl index faa4d1b..bcaa7d1 100644 --- a/openlane/digital_pll/config.tcl +++ b/openlane/digital_pll/config.tcl
@@ -10,12 +10,16 @@ set ::env(CLOCK_TREE_SYNTH) 0 set ::env(PDN_CFG) $script_dir/pdn.tcl +set ::env(FP_PDN_CORE_RING) 1 +set ::env(FP_PDN_VPITCH) 50 +set ::env(FP_PDN_HPITCH) 50 + set ::env(SYNTH_BUFFERING) 0 set ::env(SYNTH_SIZING) 0 -set ::env(CELL_PAD) 8 +set ::env(CELL_PAD) 4 -set ::env(FP_CORE_UTIL) 60 -set ::env(PL_TARGET_DENSITY) 0.60 +set ::env(FP_CORE_UTIL) 50 +set ::env(PL_TARGET_DENSITY) 0.55 set ::env(SYNTH_MAX_FANOUT) 6
diff --git a/openlane/digital_pll/pdn.tcl b/openlane/digital_pll/pdn.tcl index edd041e..c6a8d30 100644 --- a/openlane/digital_pll/pdn.tcl +++ b/openlane/digital_pll/pdn.tcl
@@ -6,13 +6,17 @@ pdngen::specify_grid stdcell { name grid - rails { + core_ring { + met3 {width $::env(FP_PDN_CORE_RING_HWIDTH) spacing $::env(FP_PDN_CORE_RING_HSPACING) core_offset $::env(FP_PDN_CORE_RING_HOFFSET)} + met4 {width $::env(FP_PDN_CORE_RING_VWIDTH) spacing $::env(FP_PDN_CORE_RING_VSPACING) core_offset $::env(FP_PDN_CORE_RING_VOFFSET)} + } + rails { met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} - } + } straps { met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} } - connect {{met1 met4}} + connect {{met1 met4} {met3 met4}} }
diff --git a/openlane/mgmt_core/config.tcl b/openlane/mgmt_core/config.tcl index af7808e..51987a9 100644 --- a/openlane/mgmt_core/config.tcl +++ b/openlane/mgmt_core/config.tcl
@@ -2,36 +2,42 @@ set ::env(DESIGN_NAME) mgmt_core -set ::env(CLOCK_PORT) "core_clk" +set ::env(CLOCK_PORT) "clock" set ::env(CLOCK_PERIOD) "50" +set ::env(SYNTH_STRATEGY) 2 set ::env(PDN_CFG) $script_dir/pdn.tcl +set ::env(FP_VERTICAL_HALO) 6 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg -#set ::env(FP_CORE_UTIL) 40 set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 2700 2000" +set ::env(DIE_AREA) "0 0 1800 1900" set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg -set ::env(PL_TARGET_DENSITY) 0.3 +set ::env(PL_TARGET_DENSITY) 0.37 set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 - +set ::env(CELL_PAD) 10 set ::env(GLB_RT_ADJUSTMENT) 0 -#set ::env(GLB_RT_TILES) 12 +set ::env(GLB_RT_TILES) 14 -set ::env(DIODE_INSERTION_STRATEGY) 1 +set ::env(DIODE_INSERTION_STRATEGY) 0 set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v\ + $script_dir/../../verilog/rtl/storage_bridge_wb.v\ $script_dir/../../verilog/rtl/clock_div.v\ $script_dir/../../verilog/rtl/caravel_clocking.v\ $script_dir/../../verilog/rtl/mgmt_core.v\ $script_dir/../../verilog/rtl/mgmt_soc.v\ $script_dir/../../verilog/rtl/housekeeping_spi.v" -# The removal of this pending the IO verilog files being parsable by yosys... -set ::env(VERILOG_FILES_BLACKBOX) "$script_dir/../../verilog/rtl/digital_pll.v" +set ::env(VERILOG_FILES_BLACKBOX) "\ + $script_dir/../../verilog/rtl/digital_pll.v" -set ::env(EXTRA_LEFS) "$script_dir/../../lef/digital_pll.lef" -set ::env(EXTRA_GDS_FILES) "$script_dir/../../gds/digital_pll.gds" +set ::env(EXTRA_LEFS) "\ + $script_dir/../../lef/digital_pll.lef" +set ::env(EXTRA_GDS_FILES) "\ + $script_dir/../../gds/digital_pll.gds" +
diff --git a/openlane/mgmt_core/macro_placement.cfg b/openlane/mgmt_core/macro_placement.cfg index a472af1..c81fd53 100644 --- a/openlane/mgmt_core/macro_placement.cfg +++ b/openlane/mgmt_core/macro_placement.cfg
@@ -1 +1 @@ -pll 665.460 756.05500 N +pll 15.225 1159.305 N
diff --git a/openlane/mgmt_core/pin_order.cfg b/openlane/mgmt_core/pin_order.cfg index 88bd4a6..db43fd6 100644 --- a/openlane/mgmt_core/pin_order.cfg +++ b/openlane/mgmt_core/pin_order.cfg
@@ -5,6 +5,7 @@ mprj.* #S +prob resetb clock flash_csb.* @@ -14,6 +15,7 @@ gpio.* #E +pwr_.* core_.* jtag.* sdo.*