text about new test
diff --git a/verilog/morphle/README.md b/verilog/morphle/README.md
index 4b223d1..d98ef7c 100644
--- a/verilog/morphle/README.md
+++ b/verilog/morphle/README.md
@@ -1,3 +1,20 @@
+<!---
+< SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
+<
+< SPDX-License-Identifier: Apache-2.0
+<
+< Licensed under the Apache License, Version 2.0 (the "License");
+< you may not use this file except in compliance with the License.
+< You may obtain a copy of the License at
+<
+< https://www.apache.org/licenses/LICENSE-2.0
+<
+< Unless required by applicable law or agreed to in writing, software
+< distributed under the License is distributed on an "AS IS" BASIS,
+< WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+< See the License for the specific language governing permissions and
+< limitations under the License.
+--->
# Tests
Each circuit in this directory is a top level simulation-only device which tests the components found in the ../verilog directory.
@@ -30,3 +47,7 @@
This tests the configuration circuit by manually shifting in 3 bits at a time and listing the outputs. It adds a comment about which state the configuration is in after the 3 bits.
A second configuration circuit is cascaded with the first in this test. Every time the first circuit has a valid configuration, the second one should have the previous valid configuration of the first circuit.
+
+### test004ycell.v
+
+A separate file, "test004.tv", has the actual test vectors as a 28 bit vector per line in the form of a 7 digit hex number. The first two bits are ignored and the rest are used as inputs to the "yellow cell" (the basic building block of Morphle Logic) or as values to be compared against the actual outputs.
