| commit | d99d3b31b1e86dd18c7aad07e3d16ea5476f25f4 | [log] [tgz] |
|---|---|---|
| author | Jecel Assumpcao Jr <jecel@merlintec.com> | Sat Nov 28 01:45:08 2020 -0300 |
| committer | Jecel Assumpcao Jr <jecel@merlintec.com> | Sat Nov 28 01:45:08 2020 -0300 |
| tree | 46bca0682d8c418ac691987c3d47860ec2e8fab7 | |
| parent | 383d5243cbc3557ce96949979ece85d15104eb20 [diff] |
text about new test
This is a combination of the Morphle Logic asynchronous runtime reconfigurable array with the Caravel project to design a chip for the Skywater 130 nm technology.
Details of each project are in their respective README files:
This version of the chip uses a single block of “yellow cells” from Morphle Logic connected to the logic analyzer pins inside Caravel. The processor in the management frame can inject a configuration into the block (a reset, configuration clock and 16 configuration bits interface with the capability of reading back 16 configuration bits coming out of the bottom of the block) and then inject a value into the top interface of the block (16 pairs of bits) and read back the value coming out the top of the block. The left, down and right interfaces are hardwired to loop back into themselves (which shouldn't matter as their missing neighbors always assert that they are “empty”).