Merge branch 'master' into develop
diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000..ecb11f5 --- /dev/null +++ b/.travis.yml
@@ -0,0 +1,39 @@ +# Copyright 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +language: minimal + +branches: + only: + - develop + - master + - staging + - /^(?i:develop)-.*$/ + +services: + - docker + +os: + - linux + +jobs: + include: + - name: "The Precheck Test" + env: TEST_SET=spm + +install: + - sh .travisCI/travisBuild.sh + +script: + - bash .travisCI/runPrecheck.sh
diff --git a/.travisCI/runPrecheck.sh b/.travisCI/runPrecheck.sh new file mode 100644 index 0000000..05bf4ad --- /dev/null +++ b/.travisCI/runPrecheck.sh
@@ -0,0 +1,24 @@ +#!/bin/bash +# Copyright 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +export TARGET_PATH=$(pwd) +cd open_mpw_precheck +docker run -it -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -u $(id -u $USER):$(id -g $USER) open_mpw_prechecker:latest bash -c "python3 open_mpw_prechecker.py -t $TARGET_PATH" +output=$TARGET_PATH/checks/full_log.log + +cnt=$(grep -c -i "DRC violations" $output) +if ! [[ $cnt ]]; then cnt=0; fi + +if [[ $cnt -eq 2 ]]; then exit 0; fi +exit 2
diff --git a/.travisCI/travisBuild.sh b/.travisCI/travisBuild.sh new file mode 100644 index 0000000..bc0c40c --- /dev/null +++ b/.travisCI/travisBuild.sh
@@ -0,0 +1,21 @@ +#!/bin/bash +# Copyright 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +export TARGET_PATH=$(pwd) +git clone https://github.com/efabless/open_mpw_precheck.git +cd open_mpw_precheck/dependencies +sh build-docker.sh +cd $TARGET_DIR +exit 0
diff --git a/mag/run_lvs_por.sh b/mag/run_lvs_por.sh new file mode 100755 index 0000000..fa69254 --- /dev/null +++ b/mag/run_lvs_por.sh
@@ -0,0 +1,9 @@ +#!/bin/sh +#-------------------------------------------------------------------------------- +# Run LVS on the simple_por layout +# +# NOTE: By specifying the testbench for the schematic-side netlist, the proper +# includes used by the testbench simulation are picked up. Otherwise, the LVS +# itself compares just the simple_por subcircuit from the testbench. +#-------------------------------------------------------------------------------- +netgen -batch lvs "simple_por.spice simple_por" "../ngspice/simple_por_tb.spice simple_por" ~/projects/efabless/tech/SW/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/mag/simple_por.mag b/mag/simple_por.mag index 2c8ff09..98c2039 100644 --- a/mag/simple_por.mag +++ b/mag/simple_por.mag
@@ -1,951 +1,604 @@ magic tech sky130A magscale 1 2 -timestamp 1605064459 +timestamp 1606075443 +<< error_s >> +rect -282 8620 -266 8678 +rect 336 8666 340 8678 +rect 348 8632 352 8666 +rect -94 8054 -82 8100 +rect 185 8074 189 8108 +<< nwell >> +rect -7877 8875 -1295 9326 +<< pwell >> +rect -7484 8100 -7428 8110 +rect -5312 7347 -5094 7557 +<< locali >> +rect -7906 9806 -7764 9819 +rect -7906 9721 -7890 9806 +rect -7778 9721 -7764 9806 +rect -7906 8982 -7764 9721 +rect -1056 9804 -813 9817 +rect -1056 9643 -1011 9804 +rect -830 9643 -813 9804 +rect -1056 8986 -813 9643 +rect -4904 8982 -813 8986 +rect -7906 8966 -813 8982 +rect -7906 8836 -1020 8966 +rect -7912 7919 -7826 8710 +rect -4904 8553 -1020 8836 +rect -837 8853 -813 8966 +rect -837 8732 2882 8853 +rect -837 8553 -813 8732 +rect -4904 8536 -813 8553 +rect -5040 8224 -813 8369 +rect -5040 7919 -4727 8224 +rect -7912 7851 -4727 7919 +rect -7912 7849 -7442 7851 +rect -7912 7723 -7899 7849 +rect -7661 7723 -7442 7849 +rect -7912 7722 -7442 7723 +rect -4996 7784 -4727 7851 +rect -1831 7919 -813 8224 +rect -1831 7784 2913 7919 +rect -4996 7722 2913 7784 +rect -7912 7674 2913 7722 +rect -7912 7344 -7258 7674 +rect -6941 7344 -6554 7560 +rect -6169 7344 -5782 7560 +rect -5397 7546 -5010 7560 +rect -5397 7360 -5299 7546 +rect -5107 7360 -5010 7546 +rect -5397 7344 -5010 7360 +rect -4625 7344 -4238 7560 +rect -3853 7344 -3466 7560 +rect -3081 7344 -2694 7560 +rect -2309 7344 -1922 7560 +rect -1537 7344 -1150 7560 +rect -765 7344 -378 7560 +rect 7 7344 394 7560 +rect 779 7344 1166 7560 +rect 1551 7344 1938 7560 +rect 2709 7344 2890 7560 +rect -7896 1696 -7713 1912 +rect -7328 1696 -6941 1912 +rect -6556 1696 -6169 1912 +rect -5784 1696 -5397 1912 +rect -5012 1696 -4625 1912 +rect -4240 1696 -3853 1912 +rect -3468 1696 -3081 1912 +rect -2696 1696 -2309 1912 +rect -1924 1696 -1537 1912 +rect -1152 1696 -765 1912 +rect -380 1696 7 1912 +rect 392 1696 779 1912 +rect 1164 1696 1551 1912 +rect 1936 1696 2323 1912 +rect 2708 1696 2888 1912 << viali >> -rect 1931 5496 1965 5530 -rect 1547 5274 1581 5308 -rect 1931 4682 1965 4716 -rect 1547 4460 1581 4494 -rect 1451 3868 1485 3902 +rect -7890 9721 -7778 9806 +rect -1011 9643 -830 9804 +rect 1277 9385 1323 9591 +rect -343 9285 -140 9332 +rect 1512 9285 1849 9332 +rect 2838 9214 2872 9410 +rect -1020 8553 -837 8966 +rect -77 8306 181 8365 +rect -7899 7723 -7661 7849 +rect -7442 7722 -4996 7851 +rect -4727 7784 -1831 8224 +rect 492 8215 559 8409 +rect 703 8251 906 8298 +rect 2323 8266 2369 8427 +rect -5299 7360 -5107 7546 +rect 2255 7129 2393 7561 << metal1 >> -rect 556 5724 3148 5749 -rect 556 5672 1298 5724 -rect 1350 5672 1362 5724 -rect 1414 5672 1426 5724 -rect 1478 5672 1490 5724 -rect 1542 5672 2162 5724 -rect 2214 5672 2226 5724 -rect 2278 5672 2290 5724 -rect 2342 5672 2354 5724 -rect 2406 5672 3148 5724 -rect 556 5647 3148 5672 -rect 764 5487 770 5539 -rect 822 5527 828 5539 -rect 1919 5530 1977 5536 -rect 1919 5527 1931 5530 -rect 822 5499 1931 5527 -rect 822 5487 828 5499 -rect 1919 5496 1931 5499 -rect 1965 5496 1977 5530 -rect 1919 5490 1977 5496 -rect 1532 5305 1538 5317 -rect 1493 5277 1538 5305 -rect 1532 5265 1538 5277 -rect 1590 5265 1596 5317 -rect 556 4910 3148 4935 -rect 556 4858 866 4910 -rect 918 4858 930 4910 -rect 982 4858 994 4910 -rect 1046 4858 1058 4910 -rect 1110 4858 1730 4910 -rect 1782 4858 1794 4910 -rect 1846 4858 1858 4910 -rect 1910 4858 1922 4910 -rect 1974 4858 2594 4910 -rect 2646 4858 2658 4910 -rect 2710 4858 2722 4910 -rect 2774 4858 2786 4910 -rect 2838 4858 3148 4910 -rect 556 4833 3148 4858 -rect 1532 4673 1538 4725 -rect 1590 4713 1596 4725 -rect 1919 4716 1977 4722 -rect 1919 4713 1931 4716 -rect 1590 4685 1931 4713 -rect 1590 4673 1596 4685 -rect 1919 4682 1931 4685 -rect 1965 4682 1977 4716 -rect 1919 4676 1977 4682 -rect 1535 4494 1593 4500 -rect 1535 4460 1547 4494 -rect 1581 4491 1593 4494 -rect 1628 4491 1634 4503 -rect 1581 4463 1634 4491 -rect 1581 4460 1593 4463 -rect 1535 4454 1593 4460 -rect 1628 4451 1634 4463 -rect 1686 4451 1692 4503 -rect 556 4096 3148 4121 -rect 556 4044 1298 4096 -rect 1350 4044 1362 4096 -rect 1414 4044 1426 4096 -rect 1478 4044 1490 4096 -rect 1542 4044 2162 4096 -rect 2214 4044 2226 4096 -rect 2278 4044 2290 4096 -rect 2342 4044 2354 4096 -rect 2406 4044 3148 4096 -rect 556 4019 3148 4044 -rect 1439 3902 1497 3908 -rect 1439 3868 1451 3902 -rect 1485 3899 1497 3902 -rect 1628 3899 1634 3911 -rect 1485 3871 1634 3899 -rect 1485 3868 1497 3871 -rect 1439 3862 1497 3868 -rect 1628 3859 1634 3871 -rect 1686 3859 1692 3911 -rect 556 3282 3148 3307 -rect 556 3230 866 3282 -rect 918 3230 930 3282 -rect 982 3230 994 3282 -rect 1046 3230 1058 3282 -rect 1110 3230 1730 3282 -rect 1782 3230 1794 3282 -rect 1846 3230 1858 3282 -rect 1910 3230 1922 3282 -rect 1974 3230 2594 3282 -rect 2646 3230 2658 3282 -rect 2710 3230 2722 3282 -rect 2774 3230 2786 3282 -rect 2838 3230 3148 3282 -rect 556 3205 3148 3230 +rect -7907 9806 -814 9817 +rect -7907 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4910 -rect 1858 4858 1910 4910 -rect 1922 4858 1974 4910 -rect 2594 4858 2646 4910 -rect 2658 4858 2710 4910 -rect 2722 4858 2774 4910 -rect 2786 4858 2838 4910 -rect 1538 4673 1590 4725 -rect 1634 4451 1686 4503 -rect 1298 4044 1350 4096 -rect 1362 4044 1414 4096 -rect 1426 4044 1478 4096 -rect 1490 4044 1542 4096 -rect 2162 4044 2214 4096 -rect 2226 4044 2278 4096 -rect 2290 4044 2342 4096 -rect 2354 4044 2406 4096 -rect 1634 3859 1686 3911 -rect 866 3230 918 3282 -rect 930 3230 982 3282 -rect 994 3230 1046 3282 -rect 1058 3230 1110 3282 -rect 1730 3230 1782 3282 -rect 1794 3230 1846 3282 -rect 1858 3230 1910 3282 -rect 1922 3230 1974 3282 -rect 2594 3230 2646 3282 -rect 2658 3230 2710 3282 -rect 2722 3230 2774 3282 -rect 2786 3230 2838 3282 +rect -7887 9732 -7778 9800 +rect -7778 9732 -7323 9800 +rect -6921 9724 -1011 9791 +rect -1011 9724 -854 9791 +rect -7228 9613 -7146 9675 +rect -7228 9075 -7146 9137 +rect -629 9684 2855 9783 +rect -5672 8534 -5596 8605 +rect 2191 9530 2343 9584 +rect 392 9279 572 9338 +rect 2806 9214 2838 9259 +rect 2838 9214 2872 9259 +rect 2872 9214 2958 9259 +rect 2806 9205 2958 9214 +rect -3616 8224 -2669 8350 +rect -5672 7991 -5597 8064 +rect -3616 7801 -2669 8224 +rect -1515 8154 -1144 8567 +rect -641 8980 396 9074 +rect 671 8980 2702 9074 +rect -776 8655 373 8830 +rect 655 8655 2803 8830 +rect 492 8215 559 8409 +rect 2560 8296 2725 8365 +rect 2286 7718 2753 7791 << metal2 >> -rect 768 8364 824 9164 -rect 782 5545 810 8364 -rect 1272 5726 1568 5749 -rect 1328 5724 1352 5726 -rect 1408 5724 1432 5726 -rect 1488 5724 1512 5726 -rect 1350 5672 1352 5724 -rect 1414 5672 1426 5724 -rect 1488 5672 1490 5724 -rect 1328 5670 1352 5672 -rect 1408 5670 1432 5672 -rect 1488 5670 1512 5672 -rect 1272 5647 1568 5670 -rect 2136 5726 2432 5749 -rect 2192 5724 2216 5726 -rect 2272 5724 2296 5726 -rect 2352 5724 2376 5726 -rect 2214 5672 2216 5724 -rect 2278 5672 2290 5724 -rect 2352 5672 2354 5724 -rect 2192 5670 2216 5672 -rect 2272 5670 2296 5672 -rect 2352 5670 2376 5672 -rect 2136 5647 2432 5670 -rect 770 5539 822 5545 -rect 770 5481 822 5487 -rect 1538 5317 1590 5323 -rect 1538 5259 1590 5265 -rect 840 4912 1136 4935 -rect 896 4910 920 4912 -rect 976 4910 1000 4912 -rect 1056 4910 1080 4912 -rect 918 4858 920 4910 -rect 982 4858 994 4910 -rect 1056 4858 1058 4910 -rect 896 4856 920 4858 -rect 976 4856 1000 4858 -rect 1056 4856 1080 4858 -rect 840 4833 1136 4856 -rect 1550 4731 1578 5259 -rect 1704 4912 2000 4935 -rect 1760 4910 1784 4912 -rect 1840 4910 1864 4912 -rect 1920 4910 1944 4912 -rect 1782 4858 1784 4910 -rect 1846 4858 1858 4910 -rect 1920 4858 1922 4910 -rect 1760 4856 1784 4858 -rect 1840 4856 1864 4858 -rect 1920 4856 1944 4858 -rect 1704 4833 2000 4856 -rect 2568 4912 2864 4935 -rect 2624 4910 2648 4912 -rect 2704 4910 2728 4912 -rect 2784 4910 2808 4912 -rect 2646 4858 2648 4910 -rect 2710 4858 2722 4910 -rect 2784 4858 2786 4910 -rect 2624 4856 2648 4858 -rect 2704 4856 2728 4858 -rect 2784 4856 2808 4858 -rect 2568 4833 2864 4856 -rect 1538 4725 1590 4731 -rect 1538 4667 1590 4673 -rect 1634 4503 1686 4509 -rect 1634 4445 1686 4451 -rect 1272 4098 1568 4121 -rect 1328 4096 1352 4098 -rect 1408 4096 1432 4098 -rect 1488 4096 1512 4098 -rect 1350 4044 1352 4096 -rect 1414 4044 1426 4096 -rect 1488 4044 1490 4096 -rect 1328 4042 1352 4044 -rect 1408 4042 1432 4044 -rect 1488 4042 1512 4044 -rect 1272 4019 1568 4042 -rect 1646 3917 1674 4445 -rect 2136 4098 2432 4121 -rect 2192 4096 2216 4098 -rect 2272 4096 2296 4098 -rect 2352 4096 2376 4098 -rect 2214 4044 2216 4096 -rect 2278 4044 2290 4096 -rect 2352 4044 2354 4096 -rect 2192 4042 2216 4044 -rect 2272 4042 2296 4044 -rect 2352 4042 2376 4044 -rect 2136 4019 2432 4042 -rect 1634 3911 1686 3917 -rect 1634 3853 1686 3859 -rect 840 3284 1136 3307 -rect 896 3282 920 3284 -rect 976 3282 1000 3284 -rect 1056 3282 1080 3284 -rect 918 3230 920 3282 -rect 982 3230 994 3282 -rect 1056 3230 1058 3282 -rect 896 3228 920 3230 -rect 976 3228 1000 3230 -rect 1056 3228 1080 3230 -rect 840 3205 1136 3228 -rect 1704 3284 2000 3307 -rect 1760 3282 1784 3284 -rect 1840 3282 1864 3284 -rect 1920 3282 1944 3284 -rect 1782 3230 1784 3282 -rect 1846 3230 1858 3282 -rect 1920 3230 1922 3282 -rect 1760 3228 1784 3230 -rect 1840 3228 1864 3230 -rect 1920 3228 1944 3230 -rect 1704 3205 2000 3228 -rect 2568 3284 2864 3307 -rect 2624 3282 2648 3284 -rect 2704 3282 2728 3284 -rect 2784 3282 2808 3284 -rect 2646 3230 2648 3282 -rect 2710 3230 2722 3282 -rect 2784 3230 2786 3282 -rect 2624 3228 2648 3230 -rect 2704 3228 2728 3230 -rect 2784 3228 2808 3230 -rect 2568 3205 2864 3228 -rect 0 0 56 800 +rect -6962 9817 -815 9818 +rect -7909 9800 -815 9817 +rect -7909 9732 -7887 9800 +rect -7323 9792 -815 9800 +rect -7909 9635 -7870 9732 +rect -7313 9718 -7061 9792 +rect -856 9791 -815 9792 +rect -854 9724 -815 9791 +rect -7313 9635 -7293 9718 +rect -7909 9592 -7293 9635 +rect -7228 9675 -7146 9685 +rect -7228 9603 -7146 9613 +rect -7081 9635 -7061 9718 +rect -856 9635 -815 9724 +rect -663 9783 2894 9809 +rect -663 9684 -629 9783 +rect 2855 9684 2894 9783 +rect -663 9656 2894 9684 +rect -7218 9147 -7162 9603 +rect -7081 9591 -815 9635 +rect 2191 9587 2343 9597 +rect 2191 9517 2343 9527 +rect 392 9338 572 9348 +rect 392 9269 572 9279 +rect -7228 9137 -7146 9147 +rect -7228 9065 -7146 9075 +rect -668 9074 427 9101 +rect -668 8980 -641 9074 +rect 396 8980 427 9074 +rect -668 8948 427 8980 +rect -806 8830 408 8855 +rect -806 8655 -776 8830 +rect 373 8655 408 8830 +rect -806 8625 408 8655 +rect -5672 8605 -5596 8615 +rect -5672 8524 -5596 8534 +rect -1540 8567 -1122 8596 +rect -5659 8074 -5607 8524 +rect -3639 8380 -2649 8399 +rect -5672 8064 -5597 8074 +rect -5672 7981 -5597 7991 +rect -3639 7801 -3616 8380 +rect -2669 7801 -2649 8380 +rect -1540 8154 -1515 8567 +rect -1144 8154 -1122 8567 +rect 496 8419 553 9269 +rect 2806 9262 2958 9272 +rect 2806 9192 2958 9202 +rect 641 9074 2720 9101 +rect 640 8980 671 9074 +rect 2702 8980 2720 9074 +rect 641 8948 2720 8980 +rect 620 8830 2851 8855 +rect 620 8655 655 8830 +rect 2803 8655 2851 8830 +rect 620 8625 2851 8655 +rect 492 8409 559 8419 +rect 492 8205 559 8215 +rect -1540 8131 -1122 8154 +rect -3639 7780 -2649 7801 +rect 2274 7801 2484 8625 +rect 2551 8296 2560 8365 +rect 2725 8296 2810 8365 +rect 2962 8296 2971 8365 +rect 2274 7791 2769 7801 +rect 2274 7718 2286 7791 +rect 2753 7718 2769 7791 +rect 2274 7707 2769 7718 << via2 >> -rect 1272 5724 1328 5726 -rect 1352 5724 1408 5726 -rect 1432 5724 1488 5726 -rect 1512 5724 1568 5726 -rect 1272 5672 1298 5724 -rect 1298 5672 1328 5724 -rect 1352 5672 1362 5724 -rect 1362 5672 1408 5724 -rect 1432 5672 1478 5724 -rect 1478 5672 1488 5724 -rect 1512 5672 1542 5724 -rect 1542 5672 1568 5724 -rect 1272 5670 1328 5672 -rect 1352 5670 1408 5672 -rect 1432 5670 1488 5672 -rect 1512 5670 1568 5672 -rect 2136 5724 2192 5726 -rect 2216 5724 2272 5726 -rect 2296 5724 2352 5726 -rect 2376 5724 2432 5726 -rect 2136 5672 2162 5724 -rect 2162 5672 2192 5724 -rect 2216 5672 2226 5724 -rect 2226 5672 2272 5724 -rect 2296 5672 2342 5724 -rect 2342 5672 2352 5724 -rect 2376 5672 2406 5724 -rect 2406 5672 2432 5724 -rect 2136 5670 2192 5672 -rect 2216 5670 2272 5672 -rect 2296 5670 2352 5672 -rect 2376 5670 2432 5672 -rect 840 4910 896 4912 -rect 920 4910 976 4912 -rect 1000 4910 1056 4912 -rect 1080 4910 1136 4912 -rect 840 4858 866 4910 -rect 866 4858 896 4910 -rect 920 4858 930 4910 -rect 930 4858 976 4910 -rect 1000 4858 1046 4910 -rect 1046 4858 1056 4910 -rect 1080 4858 1110 4910 -rect 1110 4858 1136 4910 -rect 840 4856 896 4858 -rect 920 4856 976 4858 -rect 1000 4856 1056 4858 -rect 1080 4856 1136 4858 -rect 1704 4910 1760 4912 -rect 1784 4910 1840 4912 -rect 1864 4910 1920 4912 -rect 1944 4910 2000 4912 -rect 1704 4858 1730 4910 -rect 1730 4858 1760 4910 -rect 1784 4858 1794 4910 -rect 1794 4858 1840 4910 -rect 1864 4858 1910 4910 -rect 1910 4858 1920 4910 -rect 1944 4858 1974 4910 -rect 1974 4858 2000 4910 -rect 1704 4856 1760 4858 -rect 1784 4856 1840 4858 -rect 1864 4856 1920 4858 -rect 1944 4856 2000 4858 -rect 2568 4910 2624 4912 -rect 2648 4910 2704 4912 -rect 2728 4910 2784 4912 -rect 2808 4910 2864 4912 -rect 2568 4858 2594 4910 -rect 2594 4858 2624 4910 -rect 2648 4858 2658 4910 -rect 2658 4858 2704 4910 -rect 2728 4858 2774 4910 -rect 2774 4858 2784 4910 -rect 2808 4858 2838 4910 -rect 2838 4858 2864 4910 -rect 2568 4856 2624 4858 -rect 2648 4856 2704 4858 -rect 2728 4856 2784 4858 -rect 2808 4856 2864 4858 -rect 1272 4096 1328 4098 -rect 1352 4096 1408 4098 -rect 1432 4096 1488 4098 -rect 1512 4096 1568 4098 -rect 1272 4044 1298 4096 -rect 1298 4044 1328 4096 -rect 1352 4044 1362 4096 -rect 1362 4044 1408 4096 -rect 1432 4044 1478 4096 -rect 1478 4044 1488 4096 -rect 1512 4044 1542 4096 -rect 1542 4044 1568 4096 -rect 1272 4042 1328 4044 -rect 1352 4042 1408 4044 -rect 1432 4042 1488 4044 -rect 1512 4042 1568 4044 -rect 2136 4096 2192 4098 -rect 2216 4096 2272 4098 -rect 2296 4096 2352 4098 -rect 2376 4096 2432 4098 -rect 2136 4044 2162 4096 -rect 2162 4044 2192 4096 -rect 2216 4044 2226 4096 -rect 2226 4044 2272 4096 -rect 2296 4044 2342 4096 -rect 2342 4044 2352 4096 -rect 2376 4044 2406 4096 -rect 2406 4044 2432 4096 -rect 2136 4042 2192 4044 -rect 2216 4042 2272 4044 -rect 2296 4042 2352 4044 -rect 2376 4042 2432 4044 -rect 840 3282 896 3284 -rect 920 3282 976 3284 -rect 1000 3282 1056 3284 -rect 1080 3282 1136 3284 -rect 840 3230 866 3282 -rect 866 3230 896 3282 -rect 920 3230 930 3282 -rect 930 3230 976 3282 -rect 1000 3230 1046 3282 -rect 1046 3230 1056 3282 -rect 1080 3230 1110 3282 -rect 1110 3230 1136 3282 -rect 840 3228 896 3230 -rect 920 3228 976 3230 -rect 1000 3228 1056 3230 -rect 1080 3228 1136 3230 -rect 1704 3282 1760 3284 -rect 1784 3282 1840 3284 -rect 1864 3282 1920 3284 -rect 1944 3282 2000 3284 -rect 1704 3230 1730 3282 -rect 1730 3230 1760 3282 -rect 1784 3230 1794 3282 -rect 1794 3230 1840 3282 -rect 1864 3230 1910 3282 -rect 1910 3230 1920 3282 -rect 1944 3230 1974 3282 -rect 1974 3230 2000 3282 -rect 1704 3228 1760 3230 -rect 1784 3228 1840 3230 -rect 1864 3228 1920 3230 -rect 1944 3228 2000 3230 -rect 2568 3282 2624 3284 -rect 2648 3282 2704 3284 -rect 2728 3282 2784 3284 -rect 2808 3282 2864 3284 -rect 2568 3230 2594 3282 -rect 2594 3230 2624 3282 -rect 2648 3230 2658 3282 -rect 2658 3230 2704 3282 -rect 2728 3230 2774 3282 -rect 2774 3230 2784 3282 -rect 2808 3230 2838 3282 -rect 2838 3230 2864 3282 -rect 2568 3228 2624 3230 -rect 2648 3228 2704 3230 -rect 2728 3228 2784 3230 -rect 2808 3228 2864 3230 +rect -7870 9732 -7323 9792 +rect -7323 9732 -7313 9792 +rect -7870 9635 -7313 9732 +rect -7061 9791 -856 9792 +rect -7061 9724 -6921 9791 +rect -6921 9724 -856 9791 +rect -7061 9635 -856 9724 +rect -629 9684 2855 9783 +rect 2191 9584 2343 9587 +rect 2191 9530 2343 9584 +rect 2191 9527 2343 9530 +rect -641 8980 396 9074 +rect -3616 8350 -2669 8380 +rect -3616 8053 -2669 8350 +rect -1515 8154 -1144 8567 +rect 2806 9259 2958 9262 +rect 2806 9205 2958 9259 +rect 2806 9202 2958 9205 +rect 671 8980 2702 9074 +rect 2810 8296 2962 8365 << metal3 >> -rect 1260 5730 1580 5731 -rect 1260 5666 1268 5730 -rect 1332 5666 1348 5730 -rect 1412 5666 1428 5730 -rect 1492 5666 1508 5730 -rect 1572 5666 1580 5730 -rect 1260 5665 1580 5666 -rect 2124 5730 2444 5731 -rect 2124 5666 2132 5730 -rect 2196 5666 2212 5730 -rect 2276 5666 2292 5730 -rect 2356 5666 2372 5730 -rect 2436 5666 2444 5730 -rect 2124 5665 2444 5666 -rect 828 4916 1148 4917 -rect 828 4852 836 4916 -rect 900 4852 916 4916 -rect 980 4852 996 4916 -rect 1060 4852 1076 4916 -rect 1140 4852 1148 4916 -rect 828 4851 1148 4852 -rect 1692 4916 2012 4917 -rect 1692 4852 1700 4916 -rect 1764 4852 1780 4916 -rect 1844 4852 1860 4916 -rect 1924 4852 1940 4916 -rect 2004 4852 2012 4916 -rect 1692 4851 2012 4852 -rect 2556 4916 2876 4917 -rect 2556 4852 2564 4916 -rect 2628 4852 2644 4916 -rect 2708 4852 2724 4916 -rect 2788 4852 2804 4916 -rect 2868 4852 2876 4916 -rect 2556 4851 2876 4852 -rect 1260 4102 1580 4103 -rect 1260 4038 1268 4102 -rect 1332 4038 1348 4102 -rect 1412 4038 1428 4102 -rect 1492 4038 1508 4102 -rect 1572 4038 1580 4102 -rect 1260 4037 1580 4038 -rect 2124 4102 2444 4103 -rect 2124 4038 2132 4102 -rect 2196 4038 2212 4102 -rect 2276 4038 2292 4102 -rect 2356 4038 2372 4102 -rect 2436 4038 2444 4102 -rect 2124 4037 2444 4038 -rect 3560 3862 4360 3982 -rect 828 3288 1148 3289 -rect 828 3224 836 3288 -rect 900 3224 916 3288 -rect 980 3224 996 3288 -rect 1060 3224 1076 3288 -rect 1140 3224 1148 3288 -rect 828 3223 1148 3224 -rect 1692 3288 2012 3289 -rect 1692 3224 1700 3288 -rect 1764 3224 1780 3288 -rect 1844 3224 1860 3288 -rect 1924 3224 1940 3288 -rect 2004 3224 2012 3288 -rect 1692 3223 2012 3224 -rect 2556 3288 2876 3289 -rect 2556 3224 2564 3288 -rect 2628 3224 2644 3288 -rect 2708 3224 2724 3288 -rect 2788 3224 2804 3288 -rect 2868 3224 2876 3288 -rect 2556 3223 2876 3224 +rect -7909 9792 -821 9814 +rect -7909 9775 -7870 9792 +rect -7313 9775 -7061 9792 +rect -7909 9531 -7874 9775 +rect -856 9635 -821 9792 +rect -663 9783 2894 9809 +rect -663 9684 -629 9783 +rect 2855 9684 2894 9783 +rect -663 9656 2894 9684 +rect -874 9531 -821 9635 +rect -7909 9496 -821 9531 +rect 2181 9587 2348 9595 +rect 2181 9527 2191 9587 +rect 2343 9527 2484 9587 +rect 2181 9522 2348 9527 +rect 2424 9447 2484 9527 +rect 2424 9387 3396 9447 +rect 2796 9262 2963 9270 +rect 2796 9202 2806 9262 +rect 2958 9202 2963 9262 +rect 2796 9197 2963 9202 +rect -668 9074 2720 9101 +rect -668 8980 -641 9074 +rect 2702 8980 2720 9074 +rect 2845 9082 2905 9197 +rect 2845 9022 3397 9082 +rect -668 8948 2720 8980 +rect -3836 8808 -2648 8848 +rect -3836 8380 -3597 8808 +rect -2679 8380 -2648 8808 +rect -3836 8053 -3616 8380 +rect -2669 8053 -2648 8380 +rect -1539 8567 -1122 8596 +rect -1539 8154 -1515 8567 +rect -1144 8154 -1122 8567 +rect 2800 8365 2971 8371 +rect 2800 8296 2810 8365 +rect 2962 8296 3395 8365 +rect 2800 8289 2971 8296 +rect -1539 8131 -1122 8154 +rect -3836 8025 -2648 8053 +rect -3836 7782 -3640 8025 << via3 >> -rect 1268 5726 1332 5730 -rect 1268 5670 1272 5726 -rect 1272 5670 1328 5726 -rect 1328 5670 1332 5726 -rect 1268 5666 1332 5670 -rect 1348 5726 1412 5730 -rect 1348 5670 1352 5726 -rect 1352 5670 1408 5726 -rect 1408 5670 1412 5726 -rect 1348 5666 1412 5670 -rect 1428 5726 1492 5730 -rect 1428 5670 1432 5726 -rect 1432 5670 1488 5726 -rect 1488 5670 1492 5726 -rect 1428 5666 1492 5670 -rect 1508 5726 1572 5730 -rect 1508 5670 1512 5726 -rect 1512 5670 1568 5726 -rect 1568 5670 1572 5726 -rect 1508 5666 1572 5670 -rect 2132 5726 2196 5730 -rect 2132 5670 2136 5726 -rect 2136 5670 2192 5726 -rect 2192 5670 2196 5726 -rect 2132 5666 2196 5670 -rect 2212 5726 2276 5730 -rect 2212 5670 2216 5726 -rect 2216 5670 2272 5726 -rect 2272 5670 2276 5726 -rect 2212 5666 2276 5670 -rect 2292 5726 2356 5730 -rect 2292 5670 2296 5726 -rect 2296 5670 2352 5726 -rect 2352 5670 2356 5726 -rect 2292 5666 2356 5670 -rect 2372 5726 2436 5730 -rect 2372 5670 2376 5726 -rect 2376 5670 2432 5726 -rect 2432 5670 2436 5726 -rect 2372 5666 2436 5670 -rect 836 4912 900 4916 -rect 836 4856 840 4912 -rect 840 4856 896 4912 -rect 896 4856 900 4912 -rect 836 4852 900 4856 -rect 916 4912 980 4916 -rect 916 4856 920 4912 -rect 920 4856 976 4912 -rect 976 4856 980 4912 -rect 916 4852 980 4856 -rect 996 4912 1060 4916 -rect 996 4856 1000 4912 -rect 1000 4856 1056 4912 -rect 1056 4856 1060 4912 -rect 996 4852 1060 4856 -rect 1076 4912 1140 4916 -rect 1076 4856 1080 4912 -rect 1080 4856 1136 4912 -rect 1136 4856 1140 4912 -rect 1076 4852 1140 4856 -rect 1700 4912 1764 4916 -rect 1700 4856 1704 4912 -rect 1704 4856 1760 4912 -rect 1760 4856 1764 4912 -rect 1700 4852 1764 4856 -rect 1780 4912 1844 4916 -rect 1780 4856 1784 4912 -rect 1784 4856 1840 4912 -rect 1840 4856 1844 4912 -rect 1780 4852 1844 4856 -rect 1860 4912 1924 4916 -rect 1860 4856 1864 4912 -rect 1864 4856 1920 4912 -rect 1920 4856 1924 4912 -rect 1860 4852 1924 4856 -rect 1940 4912 2004 4916 -rect 1940 4856 1944 4912 -rect 1944 4856 2000 4912 -rect 2000 4856 2004 4912 -rect 1940 4852 2004 4856 -rect 2564 4912 2628 4916 -rect 2564 4856 2568 4912 -rect 2568 4856 2624 4912 -rect 2624 4856 2628 4912 -rect 2564 4852 2628 4856 -rect 2644 4912 2708 4916 -rect 2644 4856 2648 4912 -rect 2648 4856 2704 4912 -rect 2704 4856 2708 4912 -rect 2644 4852 2708 4856 -rect 2724 4912 2788 4916 -rect 2724 4856 2728 4912 -rect 2728 4856 2784 4912 -rect 2784 4856 2788 4912 -rect 2724 4852 2788 4856 -rect 2804 4912 2868 4916 -rect 2804 4856 2808 4912 -rect 2808 4856 2864 4912 -rect 2864 4856 2868 4912 -rect 2804 4852 2868 4856 -rect 1268 4098 1332 4102 -rect 1268 4042 1272 4098 -rect 1272 4042 1328 4098 -rect 1328 4042 1332 4098 -rect 1268 4038 1332 4042 -rect 1348 4098 1412 4102 -rect 1348 4042 1352 4098 -rect 1352 4042 1408 4098 -rect 1408 4042 1412 4098 -rect 1348 4038 1412 4042 -rect 1428 4098 1492 4102 -rect 1428 4042 1432 4098 -rect 1432 4042 1488 4098 -rect 1488 4042 1492 4098 -rect 1428 4038 1492 4042 -rect 1508 4098 1572 4102 -rect 1508 4042 1512 4098 -rect 1512 4042 1568 4098 -rect 1568 4042 1572 4098 -rect 1508 4038 1572 4042 -rect 2132 4098 2196 4102 -rect 2132 4042 2136 4098 -rect 2136 4042 2192 4098 -rect 2192 4042 2196 4098 -rect 2132 4038 2196 4042 -rect 2212 4098 2276 4102 -rect 2212 4042 2216 4098 -rect 2216 4042 2272 4098 -rect 2272 4042 2276 4098 -rect 2212 4038 2276 4042 -rect 2292 4098 2356 4102 -rect 2292 4042 2296 4098 -rect 2296 4042 2352 4098 -rect 2352 4042 2356 4098 -rect 2292 4038 2356 4042 -rect 2372 4098 2436 4102 -rect 2372 4042 2376 4098 -rect 2376 4042 2432 4098 -rect 2432 4042 2436 4098 -rect 2372 4038 2436 4042 -rect 836 3284 900 3288 -rect 836 3228 840 3284 -rect 840 3228 896 3284 -rect 896 3228 900 3284 -rect 836 3224 900 3228 -rect 916 3284 980 3288 -rect 916 3228 920 3284 -rect 920 3228 976 3284 -rect 976 3228 980 3284 -rect 916 3224 980 3228 -rect 996 3284 1060 3288 -rect 996 3228 1000 3284 -rect 1000 3228 1056 3284 -rect 1056 3228 1060 3284 -rect 996 3224 1060 3228 -rect 1076 3284 1140 3288 -rect 1076 3228 1080 3284 -rect 1080 3228 1136 3284 -rect 1136 3228 1140 3284 -rect 1076 3224 1140 3228 -rect 1700 3284 1764 3288 -rect 1700 3228 1704 3284 -rect 1704 3228 1760 3284 -rect 1760 3228 1764 3284 -rect 1700 3224 1764 3228 -rect 1780 3284 1844 3288 -rect 1780 3228 1784 3284 -rect 1784 3228 1840 3284 -rect 1840 3228 1844 3284 -rect 1780 3224 1844 3228 -rect 1860 3284 1924 3288 -rect 1860 3228 1864 3284 -rect 1864 3228 1920 3284 -rect 1920 3228 1924 3284 -rect 1860 3224 1924 3228 -rect 1940 3284 2004 3288 -rect 1940 3228 1944 3284 -rect 1944 3228 2000 3284 -rect 2000 3228 2004 3284 -rect 1940 3224 2004 3228 -rect 2564 3284 2628 3288 -rect 2564 3228 2568 3284 -rect 2568 3228 2624 3284 -rect 2624 3228 2628 3284 -rect 2564 3224 2628 3228 -rect 2644 3284 2708 3288 -rect 2644 3228 2648 3284 -rect 2648 3228 2704 3284 -rect 2704 3228 2708 3284 -rect 2644 3224 2708 3228 -rect 2724 3284 2788 3288 -rect 2724 3228 2728 3284 -rect 2728 3228 2784 3284 -rect 2784 3228 2788 3284 -rect 2724 3224 2788 3228 -rect 2804 3284 2868 3288 -rect 2804 3228 2808 3284 -rect 2808 3228 2864 3284 -rect 2864 3228 2868 3284 -rect 2804 3224 2868 3228 +rect -7874 9635 -7870 9775 +rect -7870 9635 -7313 9775 +rect -7313 9635 -7061 9775 +rect -7061 9635 -874 9775 +rect -629 9684 2855 9783 +rect -7874 9531 -874 9635 +rect -641 8980 396 9074 +rect 396 8980 671 9074 +rect 671 8980 2702 9074 +rect -3597 8380 -2679 8808 +rect -3597 8089 -2679 8380 +rect -1515 8154 -1144 8567 << metal4 >> -rect 828 5358 1148 5749 -rect 828 5122 870 5358 -rect 1106 5122 1148 5358 -rect 828 4916 1148 5122 -rect 828 4852 836 4916 -rect 900 4852 916 4916 -rect 980 4852 996 4916 -rect 1060 4852 1076 4916 -rect 1140 4852 1148 4916 -rect 828 4544 1148 4852 -rect 828 4308 870 4544 -rect 1106 4308 1148 4544 -rect 828 3730 1148 4308 -rect 828 3494 870 3730 -rect 1106 3494 1148 3730 -rect 828 3288 1148 3494 -rect 828 3224 836 3288 -rect 900 3224 916 3288 -rect 980 3224 996 3288 -rect 1060 3224 1076 3288 -rect 1140 3224 1148 3288 -rect 828 3205 1148 3224 -rect 1260 5730 1580 5749 -rect 1260 5666 1268 5730 -rect 1332 5666 1348 5730 -rect 1412 5666 1428 5730 -rect 1492 5666 1508 5730 -rect 1572 5666 1580 5730 -rect 1260 4951 1580 5666 -rect 1260 4715 1302 4951 -rect 1538 4715 1580 4951 -rect 1260 4137 1580 4715 -rect 1260 4102 1302 4137 -rect 1538 4102 1580 4137 -rect 1260 4038 1268 4102 -rect 1572 4038 1580 4102 -rect 1260 3901 1302 4038 -rect 1538 3901 1580 4038 -rect 1260 3205 1580 3901 -rect 1692 5358 2012 5749 -rect 1692 5122 1734 5358 -rect 1970 5122 2012 5358 -rect 1692 4916 2012 5122 -rect 1692 4852 1700 4916 -rect 1764 4852 1780 4916 -rect 1844 4852 1860 4916 -rect 1924 4852 1940 4916 -rect 2004 4852 2012 4916 -rect 1692 4544 2012 4852 -rect 1692 4308 1734 4544 -rect 1970 4308 2012 4544 -rect 1692 3730 2012 4308 -rect 1692 3494 1734 3730 -rect 1970 3494 2012 3730 -rect 1692 3288 2012 3494 -rect 1692 3224 1700 3288 -rect 1764 3224 1780 3288 -rect 1844 3224 1860 3288 -rect 1924 3224 1940 3288 -rect 2004 3224 2012 3288 -rect 1692 3205 2012 3224 -rect 2124 5730 2444 5749 -rect 2124 5666 2132 5730 -rect 2196 5666 2212 5730 -rect 2276 5666 2292 5730 -rect 2356 5666 2372 5730 -rect 2436 5666 2444 5730 -rect 2124 4951 2444 5666 -rect 2124 4715 2166 4951 -rect 2402 4715 2444 4951 -rect 2124 4137 2444 4715 -rect 2124 4102 2166 4137 -rect 2402 4102 2444 4137 -rect 2124 4038 2132 4102 -rect 2436 4038 2444 4102 -rect 2124 3901 2166 4038 -rect 2402 3901 2444 4038 -rect 2124 3205 2444 3901 -rect 2556 5358 2876 5749 -rect 2556 5122 2598 5358 -rect 2834 5122 2876 5358 -rect 2556 4916 2876 5122 -rect 2556 4852 2564 4916 -rect 2628 4852 2644 4916 -rect 2708 4852 2724 4916 -rect 2788 4852 2804 4916 -rect 2868 4852 2876 4916 -rect 2556 4544 2876 4852 -rect 2556 4308 2598 4544 -rect 2834 4308 2876 4544 -rect 2556 3730 2876 4308 -rect 2556 3494 2598 3730 -rect 2834 3494 2876 3730 -rect 2556 3288 2876 3494 -rect 2556 3224 2564 3288 -rect 2628 3224 2644 3288 -rect 2708 3224 2724 3288 -rect 2788 3224 2804 3288 -rect 2868 3224 2876 3288 -rect 2556 3205 2876 3224 +rect -7909 9775 -821 9814 +rect -7909 9531 -7874 9775 +rect -874 9531 -821 9775 +rect -7909 9496 -821 9531 +rect -706 9783 3233 9822 +rect -706 9684 -629 9783 +rect 2855 9684 3233 9783 +rect -706 9493 3233 9684 +rect 2896 9286 3231 9305 +rect -7909 9074 2720 9186 +rect -7909 8980 -641 9074 +rect 2702 8980 2720 9074 +rect -7909 8808 2720 8980 +rect -7909 8786 -3597 8808 +rect -3930 8089 -3597 8786 +rect -2679 8786 2720 8808 +rect -2679 8089 -2648 8786 +rect 2896 8605 2932 9286 +rect -1561 8567 2932 8605 +rect -1561 8154 -1515 8567 +rect -1144 8154 2932 8567 +rect -1561 8146 2932 8154 +rect 3199 8146 3231 9286 +rect -1561 8122 3231 8146 +rect -3930 8053 -2648 8089 +rect -3930 1582 -3736 8053 << via4 >> -rect 870 5122 1106 5358 -rect 870 4308 1106 4544 -rect 870 3494 1106 3730 -rect 1302 4715 1538 4951 -rect 1302 4102 1538 4137 -rect 1302 4038 1332 4102 -rect 1332 4038 1348 4102 -rect 1348 4038 1412 4102 -rect 1412 4038 1428 4102 -rect 1428 4038 1492 4102 -rect 1492 4038 1508 4102 -rect 1508 4038 1538 4102 -rect 1302 3901 1538 4038 -rect 1734 5122 1970 5358 -rect 1734 4308 1970 4544 -rect 1734 3494 1970 3730 -rect 2166 4715 2402 4951 -rect 2166 4102 2402 4137 -rect 2166 4038 2196 4102 -rect 2196 4038 2212 4102 -rect 2212 4038 2276 4102 -rect 2276 4038 2292 4102 -rect 2292 4038 2356 4102 -rect 2356 4038 2372 4102 -rect 2372 4038 2402 4102 -rect 2166 3901 2402 4038 -rect 2598 5122 2834 5358 -rect 2598 4308 2834 4544 -rect 2598 3494 2834 3730 +rect -3597 8089 -2679 8778 +rect 2932 8146 3199 9286 << metal5 >> -rect 556 5358 3148 5400 -rect 556 5122 870 5358 -rect 1106 5122 1734 5358 -rect 1970 5122 2598 5358 -rect 2834 5122 3148 5358 -rect 556 5080 3148 5122 -rect 556 4951 3148 4993 -rect 556 4715 1302 4951 -rect 1538 4715 2166 4951 -rect 2402 4715 3148 4951 -rect 556 4673 3148 4715 -rect 556 4544 3148 4586 -rect 556 4308 870 4544 -rect 1106 4308 1734 4544 -rect 1970 4308 2598 4544 -rect 2834 4308 3148 4544 -rect 556 4266 3148 4308 -rect 556 4137 3148 4179 -rect 556 3901 1302 4137 -rect 1538 3901 2166 4137 -rect 2402 3901 3148 4137 -rect 556 3859 3148 3901 -rect 556 3730 3148 3772 -rect 556 3494 870 3730 -rect 1106 3494 1734 3730 -rect 1970 3494 2598 3730 -rect 2834 3494 3148 3730 -rect 556 3452 3148 3494 -use sky130_fd_sc_hvl__conb_1 _1_ /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag -timestamp 1604489734 -transform 1 0 1228 0 -1 4070 -box -66 -23 546 897 -use sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag -timestamp 1604489734 -transform 1 0 940 0 1 4070 +rect 2904 9286 3224 9310 +rect -3634 8778 -2648 8848 +rect -3634 8089 -3597 8778 +rect -2679 8089 -2648 8778 +rect -3634 8025 -2648 8089 +rect -3440 7666 -2648 8025 +rect 2904 8146 2932 9286 +rect 3199 8146 3224 9286 +rect 2904 7773 3224 8146 +use sky130_fd_pr__nfet_g5v0d10v5_TGFUGS sky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 +timestamp 1606063140 +transform 1 0 -6432 0 1 8300 +box -962 -458 962 458 +use sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 +timestamp 1605994897 +transform -1 0 -7576 0 1 8300 +box -308 -458 308 458 +use sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 +timestamp 1606063140 +transform 1 0 -6290 0 1 9372 +box -1101 -497 1101 497 +use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 +timestamp 1606063140 +transform 1 0 -7539 0 1 9372 +box -338 -497 338 497 +use sky130_fd_pr__nfet_g5v0d10v5_PKVMTM sky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 +timestamp 1606063140 +transform 1 0 -5287 0 1 8301 +box -308 -458 308 458 +use sky130_fd_pr__pfet_g5v0d10v5_YUHPBG sky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 +timestamp 1606063140 +transform 1 0 -5041 0 1 9372 +box -338 -497 338 497 +use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 +timestamp 1606063140 +transform 1 0 -4555 0 1 9372 +box -338 -497 338 497 +use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 +timestamp 1606063140 +transform 1 0 -4069 0 1 9372 +box -338 -497 338 497 +use sky130_fd_pr__pfet_g5v0d10v5_YEUEBV sky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 +timestamp 1606063140 +transform 1 0 -2929 0 1 9372 +box -992 -497 992 497 +use sky130_fd_pr__pfet_g5v0d10v5_YUHPXE sky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 +timestamp 1606063140 +transform 1 0 -1789 0 1 9372 +box -338 -497 338 497 +use sky130_fd_pr__pfet_g5v0d10v5_3YBPVB sky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 +timestamp 1606063140 +transform 1 0 -1303 0 1 9372 +box -338 -497 338 497 +use sky130_fd_sc_hvl__schmittbuf_1 sky130_fd_sc_hvl__schmittbuf_1_0 ~/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/mag +timestamp 1606075443 +transform 1 0 -480 0 1 7935 box -66 -23 1122 897 -use sky130_fd_sc_hvl__decap_4 FILLER_0_0 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag -timestamp 1604489734 -transform 1 0 556 0 -1 4070 +use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_0 ~/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/mag +timestamp 1606075443 +transform 1 0 576 0 1 7935 +box -66 -23 1986 897 +use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_1 +timestamp 1606075443 +transform 1 0 -470 0 1 8969 +box -66 -23 1986 897 +use sky130_fd_sc_hvl__fill_4 sky130_fd_sc_hvl__fill_4_0 ~/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/mag +timestamp 1606075443 +transform 1 0 2496 0 1 7935 box -66 -23 450 897 -use sky130_fd_sc_hvl__fill_2 FILLER_0_4 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag -timestamp 1604489734 -transform 1 0 940 0 -1 4070 -box -66 -23 258 897 -use sky130_fd_sc_hvl__fill_1 FILLER_0_6 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag -timestamp 1604489734 -transform 1 0 1132 0 -1 4070 -box -66 -23 162 897 -use sky130_fd_sc_hvl__decap_8 FILLER_0_12 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag -timestamp 1604489734 -transform 1 0 1708 0 -1 4070 -box -66 -23 834 897 -use sky130_fd_sc_hvl__decap_4 FILLER_1_0 -timestamp 1604489734 -transform 1 0 556 0 1 4070 -box -66 -23 450 897 -use sky130_fd_sc_hvl__decap_4 FILLER_0_20 -timestamp 1604489734 -transform 1 0 2476 0 -1 4070 -box -66 -23 450 897 -use sky130_fd_sc_hvl__fill_2 FILLER_0_24 -timestamp 1604489734 -transform 1 0 2860 0 -1 4070 -box -66 -23 258 897 -use sky130_fd_sc_hvl__decap_8 FILLER_1_15 -timestamp 1604489734 -transform 1 0 1996 0 1 4070 -box -66 -23 834 897 -use sky130_fd_sc_hvl__decap_4 FILLER_1_23 -timestamp 1604489734 -transform 1 0 2764 0 1 4070 -box -66 -23 450 897 -use sky130_fd_sc_hvl__fill_1 FILLER_0_26 -timestamp 1604489734 -transform 1 0 3052 0 -1 4070 -box -66 -23 162 897 -use sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 -timestamp 1604489734 -transform 1 0 940 0 -1 5698 -box -66 -23 1122 897 -use sky130_fd_sc_hvl__decap_4 FILLER_2_0 -timestamp 1604489734 -transform 1 0 556 0 -1 5698 -box -66 -23 450 897 -use sky130_fd_sc_hvl__decap_8 FILLER_2_15 -timestamp 1604489734 -transform 1 0 1996 0 -1 5698 -box -66 -23 834 897 -use sky130_fd_sc_hvl__decap_4 FILLER_2_23 -timestamp 1604489734 -transform 1 0 2764 0 -1 5698 -box -66 -23 450 897 +use sky130_fd_sc_hvl__inv_8 sky130_fd_sc_hvl__inv_8_0 ~/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/mag +timestamp 1606075443 +transform 1 0 1450 0 1 8969 +box -66 -23 1506 897 +use sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 sky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 +timestamp 1606074388 +transform 1 0 -2501 0 1 4629 +box -5446 -3098 5446 3098 +use sky130_fd_pr__cap_mim_m3_1_N249RX sky130_fd_pr__cap_mim_m3_1_N249RX_0 +timestamp 1605923309 +transform -1 0 -650 0 1 4682 +box -3186 -3100 3186 3100 +use sky130_fd_pr__cap_mim_m3_2_N249RX sky130_fd_pr__cap_mim_m3_2_N249RX_0 +timestamp 1605923309 +transform 1 0 -177 0 1 4682 +box -3379 -3101 3401 3101 << labels >> -rlabel metal2 s 768 8364 824 9164 6 porb_h -port 0 nsew default tristate -rlabel metal2 s 0 0 56 800 6 vdd3v3 -port 1 nsew default input -rlabel metal3 s 3560 3862 4360 3982 6 vss -port 2 nsew default input -rlabel metal5 s 556 3452 3148 3772 6 VPWR -port 3 nsew default input -rlabel metal5 s 556 3859 3148 4179 6 VGND -port 4 nsew default input +flabel metal2 520 8895 520 8895 0 FreeSans 320 0 0 0 out +flabel metal4 s -7909 9496 -7874 9814 0 FreeSans 320 0 0 0 vdd3v3 +port 0 nsew +flabel metal4 s -7909 8786 -7715 9186 0 FreeSans 320 0 0 0 vss +port 2 nsew +flabel metal3 3022 8296 3395 8365 0 FreeSans 320 0 0 0 porb_h +port 3 nsew +flabel metal4 s 3027 9493 3233 9822 0 FreeSans 320 0 0 0 vdd1v8 +port 1 nsew +flabel metal3 3242 9022 3397 9082 0 FreeSans 320 0 0 0 por_l +port 4 nsew +flabel metal3 3241 9387 3396 9447 0 FreeSans 320 0 0 0 porb_l +port 5 nsew << properties >> string FIXED_BBOX 0 0 4360 9164 << end >>
diff --git a/mag/simple_por.spice b/mag/simple_por.spice new file mode 100644 index 0000000..fe583f8 --- /dev/null +++ b/mag/simple_por.spice
@@ -0,0 +1,215 @@ +* NGSPICE file created from simple_por.ext - technology: sky130A + +.subckt sky130_fd_sc_hvl__buf_8 A VGND VNB VPB VPWR X +X0 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X1 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X2 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X3 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X4 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X5 a_45_443# A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X6 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X7 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X8 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X9 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X10 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X11 X a_45_443# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X12 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X13 VPWR a_45_443# X VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X14 VPWR A a_45_443# VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X15 a_45_443# A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X16 VGND A a_45_443# VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X17 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X18 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X19 VGND a_45_443# X VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X20 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X21 X a_45_443# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +.ends + +.subckt sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ VSUBS a_n465_n200# a_n247_n200# a_n29_n200# ++ a_843_n200# w_n1101_n497# a_n843_n297# a_625_n200# a_683_n297# a_n625_n297# a_407_n200# ++ a_465_n297# a_n407_n297# a_247_n297# a_n901_n200# a_189_n200# a_29_n297# a_n189_n297# ++ a_n683_n200# +X0 a_407_n200# a_247_n297# a_189_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X1 a_843_n200# a_683_n297# a_625_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X2 a_n465_n200# a_n625_n297# a_n683_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X3 a_189_n200# a_29_n297# a_n29_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X4 a_625_n200# a_465_n297# a_407_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X5 a_n247_n200# a_n407_n297# a_n465_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X6 a_n683_n200# a_n843_n297# a_n901_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X7 a_n29_n200# a_n189_n297# a_n247_n200# w_n1101_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__nfet_g5v0d10v5_TGFUGS VSUBS a_n80_n288# a_n574_n200# a_n356_n200# ++ a_n138_n200# a_n734_n288# a_574_n288# a_n516_n288# a_356_n288# a_80_n200# a_n298_n288# ++ a_138_n288# w_n962_n458# a_734_n200# a_516_n200# a_298_n200# a_n792_n200# +X0 a_516_n200# a_356_n288# a_298_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +X1 a_n574_n200# a_n734_n288# a_n792_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +X2 a_298_n200# a_138_n288# a_80_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +X3 a_80_n200# a_n80_n288# a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +X4 a_734_n200# a_574_n288# a_516_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +X5 a_n356_n200# a_n516_n288# a_n574_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +X6 a_n138_n200# a_n298_n288# a_n356_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 VSUBS a_n2578_n2932# a_5142_2500# a_n1034_n2932# ++ a_n262_2500# a_1668_2500# a_n262_n2932# a_n3736_2500# a_3984_n2932# a_n2192_2500# ++ a_3984_2500# a_2440_n2932# a_2440_2500# a_4370_n2932# a_3598_2500# a_2054_2500# ++ a_n4508_n2932# a_510_2500# a_n4122_2500# a_n2964_n2932# a_124_2500# a_n4894_n2932# ++ a_1282_n2932# a_124_n2932# a_n1420_n2932# a_4370_2500# a_n3350_n2932# a_n648_n2932# ++ a_n648_2500# a_n5280_n2932# a_n1420_2500# a_n2964_2500# a_n2578_2500# a_n1034_2500# ++ a_2826_n2932# a_n2192_n2932# a_2826_2500# a_4756_n2932# w_n5446_n3098# a_1282_2500# ++ a_3212_n2932# a_n4894_2500# a_n3350_2500# a_n4508_2500# a_5142_n2932# a_896_2500# ++ a_510_n2932# a_1668_n2932# a_n1806_n2932# a_4756_2500# a_n3736_n2932# a_3598_n2932# ++ a_3212_2500# a_2054_n2932# a_896_n2932# a_n5280_2500# a_n4122_n2932# a_n1806_2500# +X0 a_n3350_n2932# a_n3350_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X1 a_n4508_n2932# a_n4508_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X2 a_n2578_n2932# a_n2578_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X3 a_n1420_n2932# a_n1420_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X4 a_n4894_n2932# a_n4894_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X5 a_n3736_n2932# a_n3736_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X6 a_3598_n2932# a_3598_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X7 a_124_n2932# a_124_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X8 a_4756_n2932# a_4756_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X9 a_n2964_n2932# a_n2964_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X10 a_1668_n2932# a_1668_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X11 a_n1806_n2932# a_n1806_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X12 a_n648_n2932# a_n648_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X13 a_3984_n2932# a_3984_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X14 a_2826_n2932# a_2826_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X15 a_510_n2932# a_510_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X16 a_n4122_n2932# a_n4122_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X17 a_n2192_n2932# a_n2192_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X18 a_5142_n2932# a_5142_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X19 a_n1034_n2932# a_n1034_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X20 a_2054_n2932# a_2054_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X21 a_4370_n2932# a_4370_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X22 a_3212_n2932# a_3212_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X23 a_1282_n2932# a_1282_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X24 a_n262_n2932# a_n262_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X25 a_n5280_n2932# a_n5280_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X26 a_2440_n2932# a_2440_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +X27 a_896_n2932# a_896_2500# VSUBS sky130_fd_pr__res_xhigh_po_0p69 w=690000u l=2.5e+07u +.ends + +.subckt sky130_fd_pr__pfet_g5v0d10v5_3YBPVB VSUBS a_n138_n200# w_n338_n497# a_80_n200# ++ a_n80_n297# +X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__cap_mim_m3_2_N249RX VSUBS c2_n3279_n3000# m4_n3379_n3100# +X0 c2_n3279_n3000# m4_n3379_n3100# sky130_fd_pr__cap_mim_m3_2 l=3e+07u w=3e+07u +.ends + +.subckt sky130_fd_sc_hvl__schmittbuf_1 A VGND VNB VPB VPWR X +R0 a_64_207# VPWR sky130_fd_pr__res_generic_pd__hv w=290000u l=3.11e+06u +X0 a_231_463# A a_117_181# VPB sky130_fd_pr__pfet_g5v0d10v5 w=750000u l=500000u +X1 a_217_207# A a_117_181# VNB sky130_fd_pr__nfet_g5v0d10v5 w=420000u l=500000u +X2 VPWR A a_231_463# VPB sky130_fd_pr__pfet_g5v0d10v5 w=750000u l=500000u +X3 a_217_207# a_117_181# a_64_207# VNB sky130_fd_pr__nfet_g5v0d10v5 w=420000u l=500000u +X4 X a_117_181# VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +R1 a_78_463# VGND sky130_fd_pr__res_generic_nd__hv w=290000u l=1.355e+06u +X5 X a_117_181# VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X6 VGND A a_217_207# VNB sky130_fd_pr__nfet_g5v0d10v5 w=420000u l=500000u +X7 a_231_463# a_117_181# a_78_463# VPB sky130_fd_pr__pfet_g5v0d10v5 w=750000u l=500000u +.ends + +.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPXE VSUBS a_n138_n200# w_n338_n497# a_80_n200# ++ a_n80_n297# +X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__nfet_g5v0d10v5_PKVMTM VSUBS a_n80_n288# a_n138_n200# a_80_n200# ++ w_n308_n458# +X0 a_80_n200# a_n80_n288# a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC VSUBS a_n80_n288# a_n138_n200# a_80_n200# ++ w_n308_n458# +X0 a_80_n200# a_n80_n288# a_n138_n200# VSUBS sky130_fd_pr__nfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__cap_mim_m3_1_N249RX VSUBS m3_n3186_n3100# c1_n3086_n3000# +X0 c1_n3086_n3000# m3_n3186_n3100# sky130_fd_pr__cap_mim_m3_1 l=3e+07u w=3e+07u +.ends + +.subckt sky130_fd_pr__pfet_g5v0d10v5_YEUEBV VSUBS w_n992_n497# a_n574_n200# a_n356_n200# ++ a_n138_n200# a_80_n200# a_n80_n297# a_734_n200# a_n734_n297# a_516_n200# a_574_n297# ++ a_n516_n297# a_356_n297# a_298_n200# a_n298_n297# a_138_n297# a_n792_n200# +X0 a_734_n200# a_574_n297# a_516_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X1 a_n356_n200# a_n516_n297# a_n574_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X2 a_n138_n200# a_n298_n297# a_n356_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X3 a_516_n200# a_356_n297# a_298_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X4 a_n574_n200# a_n734_n297# a_n792_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X5 a_298_n200# a_138_n297# a_80_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +X6 a_80_n200# a_n80_n297# a_n138_n200# w_n992_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_pr__pfet_g5v0d10v5_YUHPBG VSUBS a_n138_n200# w_n338_n497# a_80_n200# ++ a_n80_n297# +X0 a_80_n200# a_n80_n297# a_n138_n200# w_n338_n497# sky130_fd_pr__pfet_g5v0d10v5 w=2e+06u l=800000u +.ends + +.subckt sky130_fd_sc_hvl__inv_8 A VGND VNB VPB VPWR Y +X0 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X1 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X2 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X3 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X4 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X5 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X6 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X7 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X8 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X9 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X10 Y A VPWR VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X11 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X12 VPWR A Y VPB sky130_fd_pr__pfet_g5v0d10v5 w=1.5e+06u l=500000u +X13 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X14 VGND A Y VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +X15 Y A VGND VNB sky130_fd_pr__nfet_g5v0d10v5 w=750000u l=500000u +.ends + +.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l +Xsky130_fd_sc_hvl__buf_8_1 out vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 +Xsky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ_0 vss vdd3v3 m1_n7445_9184# vdd3v3 vdd3v3 vdd3v3 ++ m1_n7445_9184# m1_n7445_9184# m1_n7445_9184# m1_n7445_9184# vdd3v3 m1_n7445_9184# ++ m1_n7445_9184# m1_n7445_9184# vdd3v3 m1_n7445_9184# m1_n7445_9184# m1_n7445_9184# ++ m1_n7445_9184# sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ +Xsky130_fd_pr__nfet_g5v0d10v5_TGFUGS_0 vss m1_n7226_8346# vss m1_n7226_8346# vss m1_n7226_8346# ++ m1_n7226_8346# m1_n7226_8346# m1_n7226_8346# m1_n7226_8346# m1_n7226_8346# m1_n7226_8346# ++ vss vss m1_n7226_8346# vss m1_n7226_8346# sky130_fd_pr__nfet_g5v0d10v5_TGFUGS +Xsky130_fd_pr__res_xhigh_po_0p69_S5N9F3_0 vss li_n5012_1696# vss li_n3468_1696# li_n3081_7344# ++ li_n765_7344# li_n2696_1696# li_n6169_7344# li_1164_1696# li_n4625_7344# li_1551_7344# ++ li_n380_1696# li_7_7344# li_1936_1696# li_779_7344# li_n765_7344# li_n7328_1696# ++ li_n2309_7344# li_n6941_7344# li_n5784_1696# li_n2309_7344# li_n7328_1696# li_n1152_1696# ++ li_n2696_1696# li_n4240_1696# li_1551_7344# li_n5784_1696# li_n3468_1696# li_n3081_7344# ++ vss li_n3853_7344# li_n5397_7344# li_n5397_7344# li_n3853_7344# li_392_1696# li_n5012_1696# ++ li_7_7344# li_1936_1696# vss li_n1537_7344# li_392_1696# vss li_n6169_7344# li_n6941_7344# ++ vss li_n1537_7344# li_n1924_1696# li_n1152_1696# li_n4240_1696# vdd3v3 li_n6556_1696# ++ li_1164_1696# li_779_7344# li_n380_1696# li_n1924_1696# vss li_n6556_1696# li_n4625_7344# ++ sky130_fd_pr__res_xhigh_po_0p69_S5N9F3 +Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_0 vss m1_n4954_9189# vdd3v3 m1_n7226_8346# m1_n7762_8104# ++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB +Xsky130_fd_pr__cap_mim_m3_2_N249RX_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_2_N249RX +Xsky130_fd_sc_hvl__schmittbuf_1_0 sky130_fd_sc_hvl__schmittbuf_1_0/A vss vss vdd3v3 ++ vdd3v3 out sky130_fd_sc_hvl__schmittbuf_1 +Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_1 vss m1_n5191_8104# vdd3v3 m1_n3664_9612# m1_n5191_8104# ++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB +Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_2 vss m1_n1698_9221# vdd3v3 sky130_fd_sc_hvl__schmittbuf_1_0/A ++ m1_n5191_8104# sky130_fd_pr__pfet_g5v0d10v5_3YBPVB +Xsky130_fd_pr__pfet_g5v0d10v5_3YBPVB_3 vss m1_n7762_8104# vdd3v3 m1_n7445_9184# m1_n7762_8104# ++ sky130_fd_pr__pfet_g5v0d10v5_3YBPVB +Xsky130_fd_pr__pfet_g5v0d10v5_YUHPXE_0 vss vdd3v3 vdd3v3 m1_n1698_9221# m1_n3664_9612# ++ sky130_fd_pr__pfet_g5v0d10v5_YUHPXE +Xsky130_fd_pr__nfet_g5v0d10v5_PKVMTM_0 vss m1_n7226_8346# vss m1_n5191_8104# vss sky130_fd_pr__nfet_g5v0d10v5_PKVMTM +Xsky130_fd_pr__nfet_g5v0d10v5_ZK8HQC_1 vss li_n5397_7344# vss m1_n7762_8104# vss sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC +Xsky130_fd_pr__cap_mim_m3_1_N249RX_0 vss vss sky130_fd_sc_hvl__schmittbuf_1_0/A sky130_fd_pr__cap_mim_m3_1_N249RX +Xsky130_fd_pr__pfet_g5v0d10v5_YEUEBV_0 vss vdd3v3 m1_n3664_9612# vdd3v3 m1_n3664_9612# ++ vdd3v3 m1_n3664_9612# m1_n3664_9612# m1_n3664_9612# vdd3v3 m1_n3664_9612# m1_n3664_9612# ++ m1_n3664_9612# m1_n3664_9612# m1_n3664_9612# m1_n3664_9612# vdd3v3 sky130_fd_pr__pfet_g5v0d10v5_YEUEBV +Xsky130_fd_pr__pfet_g5v0d10v5_YUHPBG_0 vss vdd3v3 vdd3v3 m1_n4954_9189# m1_n7445_9184# ++ sky130_fd_pr__pfet_g5v0d10v5_YUHPBG +Xsky130_fd_sc_hvl__inv_8_0 out vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 +Xsky130_fd_sc_hvl__fill_4_0 vss vss vdd3v3 vdd3v3 sky130_fd_sc_hvl__fill_4 +Xsky130_fd_sc_hvl__buf_8_0 out vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 +.ends +
diff --git a/mag/sky130_fd_pr__cap_mim_m3_1_N249RX.mag b/mag/sky130_fd_pr__cap_mim_m3_1_N249RX.mag new file mode 100644 index 0000000..790d2b3 --- /dev/null +++ b/mag/sky130_fd_pr__cap_mim_m3_1_N249RX.mag
@@ -0,0 +1,33 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1605923309 +<< metal3 >> +rect -3186 3072 3186 3100 +rect -3186 -3072 3102 3072 +rect 3166 -3072 3186 3072 +rect -3186 -3100 3186 -3072 +<< via3 >> +rect 3102 -3072 3166 3072 +<< mimcap >> +rect -3086 2960 2914 3000 +rect -3086 -2960 -3046 2960 +rect 2874 -2960 2914 2960 +rect -3086 -3000 2914 -2960 +<< mimcapcontact >> +rect -3046 -2960 2874 2960 +<< metal4 >> +rect 3086 3072 3182 3088 +rect -3047 2960 2875 2961 +rect -3047 -2960 -3046 2960 +rect 2874 -2960 2875 2960 +rect -3047 -2961 2875 -2960 +rect 3086 -3072 3102 3072 +rect 3166 -3072 3182 3072 +rect 3086 -3088 3182 -3072 +<< properties >> +string gencell sky130_fd_pr__cap_mim_m3_1 +string FIXED_BBOX -3186 -3100 3014 3100 +string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__cap_mim_m3_2_N249RX.mag b/mag/sky130_fd_pr__cap_mim_m3_2_N249RX.mag new file mode 100644 index 0000000..164a799 --- /dev/null +++ b/mag/sky130_fd_pr__cap_mim_m3_2_N249RX.mag
@@ -0,0 +1,33 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1605923309 +<< metal4 >> +rect -3379 3059 3379 3100 +rect -3379 -3059 3123 3059 +rect 3359 -3059 3379 3059 +rect -3379 -3100 3379 -3059 +<< via4 >> +rect 3123 -3059 3359 3059 +<< mimcap2 >> +rect -3279 2960 2721 3000 +rect -3279 -2960 -3239 2960 +rect 2681 -2960 2721 2960 +rect -3279 -3000 2721 -2960 +<< mimcap2contact >> +rect -3239 -2960 2681 2960 +<< metal5 >> +rect 3081 3059 3401 3101 +rect -3263 2960 2705 2984 +rect -3263 -2960 -3239 2960 +rect 2681 -2960 2705 2960 +rect -3263 -2984 2705 -2960 +rect 3081 -3059 3123 3059 +rect 3359 -3059 3401 3059 +rect 3081 -3101 3401 -3059 +<< properties >> +string gencell sky130_fd_pr__cap_mim_m3_2 +string FIXED_BBOX -3379 -3100 2821 3100 +string parameters w 30.00 l 30.00 val 920.4 carea 1.00 cperi 0.17 nx 1 ny 1 dummy 0 square 0 lmin 2.00 wmin 2.00 lmax 30.0 wmax 30.0 dc 0 bconnect 1 tconnect 1 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_1kamgc.mag b/mag/sky130_fd_pr__nfet_01v8_1kamgc.mag deleted file mode 100644 index 5f8ae05..0000000 --- a/mag/sky130_fd_pr__nfet_01v8_1kamgc.mag +++ /dev/null
@@ -1,80 +0,0 @@ -magic -tech sky130A -magscale 1 2 -timestamp 1603919870 -<< error_p >> -rect -79 208 79 224 -rect -79 182 79 190 -rect -175 -120 -167 120 -rect -149 -120 -133 120 -rect 141 -120 149 120 -rect 167 -120 183 120 -rect -79 -190 79 -174 -rect -79 -216 79 -208 -<< pwell >> -rect -211 -252 211 252 -<< nmos >> -rect -15 -42 15 42 -<< ndiff >> -rect -73 30 -15 42 -rect -73 -30 -61 30 -rect -27 -30 -15 30 -rect -73 -42 -15 -30 -rect 15 30 73 42 -rect 15 -30 27 30 -rect 61 -30 73 30 -rect 15 -42 73 -30 -<< ndiffc >> -rect -61 -30 -27 30 -rect 27 -30 61 30 -<< psubdiff >> -rect -175 182 -79 216 -rect 79 182 175 216 -rect -175 120 -141 182 -rect 141 120 175 182 -rect -175 -182 -141 -120 -rect 141 -182 175 -120 -rect -175 -216 -79 -182 -rect 79 -216 175 -182 -<< psubdiffcont >> -rect -79 182 79 216 -rect -175 -120 -141 120 -rect 141 -120 175 120 -rect -79 -216 79 -182 -<< poly >> -rect -33 114 33 130 -rect -33 80 -17 114 -rect 17 80 33 114 -rect -33 64 33 80 -rect -15 42 15 64 -rect -15 -64 15 -42 -rect -33 -80 33 -64 -rect -33 -114 -17 -80 -rect 17 -114 33 -80 -rect -33 -130 33 -114 -<< polycont >> -rect -17 80 17 114 -rect -17 -114 17 -80 -<< locali >> -rect -175 182 -79 216 -rect 79 182 175 216 -rect -175 120 -141 182 -rect 141 120 175 182 -rect -33 80 -17 114 -rect 17 80 33 114 -rect -61 30 -27 46 -rect -61 -46 -27 -30 -rect 27 30 61 46 -rect 27 -46 61 -30 -rect -33 -114 -17 -80 -rect 17 -114 33 -80 -rect -175 -182 -141 -120 -rect 141 -182 175 -120 -rect -175 -216 -79 -182 -rect 79 -216 175 -182 -<< properties >> -string gencell sky130_fd_pr__nfet_01v8 -string FIXED_BBOX -158 -199 158 199 -string parameters w 0.420 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 -string library sky130 -<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag new file mode 100644 index 0000000..7be65d4 --- /dev/null +++ b/mag/sky130_fd_pr__nfet_g5v0d10v5_PKVMTM.mag
@@ -0,0 +1,98 @@ +magic +tech sky130A +timestamp 1606063140 +<< pwell >> +rect -154 -229 154 229 +<< mvnmos >> +rect -40 -100 40 100 +<< mvndiff >> +rect -69 94 -40 100 +rect -69 -94 -63 94 +rect -46 -94 -40 94 +rect -69 -100 -40 -94 +rect 40 94 69 100 +rect 40 -94 46 94 +rect 63 -94 69 94 +rect 40 -100 69 -94 +<< mvndiffc >> +rect -63 -94 -46 94 +rect 46 -94 63 94 +<< mvpsubdiff >> +rect -136 205 136 211 +rect -136 188 -82 205 +rect 82 188 136 205 +rect -136 182 136 188 +rect -136 -182 -107 182 +rect 107 157 136 182 +rect 107 -157 113 157 +rect 130 -157 136 157 +rect 107 -182 136 -157 +rect -136 -188 136 -182 +rect -136 -205 -82 -188 +rect 82 -205 136 -188 +rect -136 -211 136 -205 +<< mvpsubdiffcont >> +rect -82 188 82 205 +rect 113 -157 130 157 +rect -82 -205 82 -188 +<< poly >> +rect -40 136 40 144 +rect -40 119 -32 136 +rect 32 119 40 136 +rect -40 100 40 119 +rect -40 -119 40 -100 +rect -40 -136 -32 -119 +rect 32 -136 40 -119 +rect -40 -144 40 -136 +<< polycont >> +rect -32 119 32 136 +rect -32 -136 32 -119 +<< locali >> +rect -130 188 -82 205 +rect 82 188 130 205 +rect -130 -19 -113 188 +rect 113 157 130 188 +rect -40 119 -32 136 +rect 32 119 40 136 +rect -63 94 -46 102 +rect -63 -102 -46 -94 +rect 46 94 63 102 +rect 46 -102 63 -94 +rect -40 -136 -32 -119 +rect 32 -136 40 -119 +rect 113 -188 130 -157 +rect -130 -205 -82 -188 +rect 82 -205 130 -188 +<< viali >> +rect -32 119 32 136 +rect -130 -188 -113 -19 +rect -63 -94 -46 94 +rect 46 -94 63 94 +rect -32 -136 32 -119 +<< metal1 >> +rect -38 136 38 139 +rect -38 119 -32 136 +rect 32 119 38 136 +rect -38 116 38 119 +rect -66 94 -43 100 +rect -133 -19 -110 -13 +rect -133 -188 -130 -19 +rect -113 -188 -110 -19 +rect -66 -94 -63 94 +rect -46 -94 -43 94 +rect -66 -100 -43 -94 +rect 43 94 66 100 +rect 43 -94 46 94 +rect 63 -94 66 94 +rect 43 -100 66 -94 +rect -38 -119 38 -116 +rect -38 -136 -32 -119 +rect 32 -136 38 -119 +rect -38 -139 38 -136 +rect -133 -194 -110 -188 +<< properties >> +string gencell sky130_fd_pr__nfet_g5v0d10v5 +string FIXED_BBOX -121 -196 121 196 +string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl +45 viagt 0 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag new file mode 100644 index 0000000..0fc9bf5 --- /dev/null +++ b/mag/sky130_fd_pr__nfet_g5v0d10v5_TGFUGS.mag
@@ -0,0 +1,326 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606063140 +<< pwell >> +rect -962 -458 962 458 +<< mvnmos >> +rect -734 -200 -574 200 +rect -516 -200 -356 200 +rect -298 -200 -138 200 +rect -80 -200 80 200 +rect 138 -200 298 200 +rect 356 -200 516 200 +rect 574 -200 734 200 +<< mvndiff >> +rect -792 188 -734 200 +rect -792 -188 -780 188 +rect -746 -188 -734 188 +rect -792 -200 -734 -188 +rect -574 188 -516 200 +rect -574 -188 -562 188 +rect -528 -188 -516 188 +rect -574 -200 -516 -188 +rect -356 188 -298 200 +rect -356 -188 -344 188 +rect -310 -188 -298 188 +rect -356 -200 -298 -188 +rect -138 188 -80 200 +rect -138 -188 -126 188 +rect -92 -188 -80 188 +rect -138 -200 -80 -188 +rect 80 188 138 200 +rect 80 -188 92 188 +rect 126 -188 138 188 +rect 80 -200 138 -188 +rect 298 188 356 200 +rect 298 -188 310 188 +rect 344 -188 356 188 +rect 298 -200 356 -188 +rect 516 188 574 200 +rect 516 -188 528 188 +rect 562 -188 574 188 +rect 516 -200 574 -188 +rect 734 188 792 200 +rect 734 -188 746 188 +rect 780 -188 792 188 +rect 734 -200 792 -188 +<< mvndiffc >> +rect -780 -188 -746 188 +rect -562 -188 -528 188 +rect -344 -188 -310 188 +rect -126 -188 -92 188 +rect 92 -188 126 188 +rect 310 -188 344 188 +rect 528 -188 562 188 +rect 746 -188 780 188 +<< mvpsubdiff >> +rect -926 410 926 422 +rect -926 376 -818 410 +rect 818 376 926 410 +rect -926 364 926 376 +rect -926 314 -868 364 +rect -926 -314 -914 314 +rect -880 -314 -868 314 +rect 868 314 926 364 +rect -926 -364 -868 -314 +rect 868 -314 880 314 +rect 914 -314 926 314 +rect 868 -364 926 -314 +rect -926 -376 926 -364 +rect -926 -410 -818 -376 +rect 818 -410 926 -376 +rect -926 -422 926 -410 +<< mvpsubdiffcont >> +rect -818 376 818 410 +rect -914 -314 -880 314 +rect 880 -314 914 314 +rect -818 -410 818 -376 +<< poly >> +rect -734 272 -574 288 +rect -734 238 -718 272 +rect -590 238 -574 272 +rect -734 200 -574 238 +rect -516 272 -356 288 +rect -516 238 -500 272 +rect -372 238 -356 272 +rect -516 200 -356 238 +rect -298 272 -138 288 +rect -298 238 -282 272 +rect -154 238 -138 272 +rect -298 200 -138 238 +rect -80 272 80 288 +rect -80 238 -64 272 +rect 64 238 80 272 +rect -80 200 80 238 +rect 138 272 298 288 +rect 138 238 154 272 +rect 282 238 298 272 +rect 138 200 298 238 +rect 356 272 516 288 +rect 356 238 372 272 +rect 500 238 516 272 +rect 356 200 516 238 +rect 574 272 734 288 +rect 574 238 590 272 +rect 718 238 734 272 +rect 574 200 734 238 +rect -734 -238 -574 -200 +rect -734 -272 -718 -238 +rect -590 -272 -574 -238 +rect -734 -288 -574 -272 +rect -516 -238 -356 -200 +rect -516 -272 -500 -238 +rect -372 -272 -356 -238 +rect -516 -288 -356 -272 +rect -298 -238 -138 -200 +rect -298 -272 -282 -238 +rect -154 -272 -138 -238 +rect -298 -288 -138 -272 +rect -80 -238 80 -200 +rect -80 -272 -64 -238 +rect 64 -272 80 -238 +rect -80 -288 80 -272 +rect 138 -238 298 -200 +rect 138 -272 154 -238 +rect 282 -272 298 -238 +rect 138 -288 298 -272 +rect 356 -238 516 -200 +rect 356 -272 372 -238 +rect 500 -272 516 -238 +rect 356 -288 516 -272 +rect 574 -238 734 -200 +rect 574 -272 590 -238 +rect 718 -272 734 -238 +rect 574 -288 734 -272 +<< polycont >> +rect -718 238 -590 272 +rect -500 238 -372 272 +rect -282 238 -154 272 +rect -64 238 64 272 +rect 154 238 282 272 +rect 372 238 500 272 +rect 590 238 718 272 +rect -718 -272 -590 -238 +rect -500 -272 -372 -238 +rect -282 -272 -154 -238 +rect -64 -272 64 -238 +rect 154 -272 282 -238 +rect 372 -272 500 -238 +rect 590 -272 718 -238 +<< locali >> +rect -914 376 -818 410 +rect 818 376 914 410 +rect -914 314 -880 376 +rect 880 314 914 376 +rect -734 238 -718 272 +rect -590 238 -574 272 +rect -516 238 -500 272 +rect -372 238 -356 272 +rect -298 238 -282 272 +rect -154 238 -138 272 +rect -80 238 -64 272 +rect 64 238 80 272 +rect 138 238 154 272 +rect 282 238 298 272 +rect 356 238 372 272 +rect 500 238 516 272 +rect 574 238 590 272 +rect 718 238 734 272 +rect -780 188 -746 204 +rect -780 -204 -746 -188 +rect -562 188 -528 204 +rect -562 -204 -528 -188 +rect -344 188 -310 204 +rect -344 -204 -310 -188 +rect -126 188 -92 204 +rect -126 -204 -92 -188 +rect 92 188 126 204 +rect 92 -204 126 -188 +rect 310 188 344 204 +rect 310 -204 344 -188 +rect 528 188 562 204 +rect 528 -204 562 -188 +rect 746 188 780 204 +rect 746 -204 780 -188 +rect -734 -272 -718 -238 +rect -590 -272 -574 -238 +rect -516 -272 -500 -238 +rect -372 -272 -356 -238 +rect -298 -272 -282 -238 +rect -154 -272 -138 -238 +rect -80 -272 -64 -238 +rect 64 -272 80 -238 +rect 138 -272 154 -238 +rect 282 -272 298 -238 +rect 356 -272 372 -238 +rect 500 -272 516 -238 +rect 574 -272 590 -238 +rect 718 -272 734 -238 +rect -914 -376 -880 -314 +rect 880 -376 914 -314 +rect -914 -410 -818 -376 +rect 818 -410 914 -376 +<< viali >> +rect -914 -263 -880 263 +rect -718 238 -590 272 +rect -500 238 -372 272 +rect -282 238 -154 272 +rect -64 238 64 272 +rect 154 238 282 272 +rect 372 238 500 272 +rect 590 238 718 272 +rect -780 21 -746 171 +rect -562 -171 -528 -21 +rect -344 21 -310 171 +rect -126 -171 -92 -21 +rect 92 21 126 171 +rect 310 -171 344 -21 +rect 528 21 562 171 +rect 746 -171 780 -21 +rect -718 -272 -590 -238 +rect -500 -272 -372 -238 +rect -282 -272 -154 -238 +rect -64 -272 64 -238 +rect 154 -272 282 -238 +rect 372 -272 500 -238 +rect 590 -272 718 -238 +<< metal1 >> +rect -920 263 -874 275 +rect -920 -263 -914 263 +rect -880 -263 -874 263 +rect -730 272 -578 278 +rect -730 238 -718 272 +rect -590 238 -578 272 +rect -730 232 -578 238 +rect -512 272 -360 278 +rect -512 238 -500 272 +rect -372 238 -360 272 +rect -512 232 -360 238 +rect -294 272 -142 278 +rect -294 238 -282 272 +rect -154 238 -142 272 +rect -294 232 -142 238 +rect -76 272 76 278 +rect -76 238 -64 272 +rect 64 238 76 272 +rect -76 232 76 238 +rect 142 272 294 278 +rect 142 238 154 272 +rect 282 238 294 272 +rect 142 232 294 238 +rect 360 272 512 278 +rect 360 238 372 272 +rect 500 238 512 272 +rect 360 232 512 238 +rect 578 272 730 278 +rect 578 238 590 272 +rect 718 238 730 272 +rect 578 232 730 238 +rect -786 171 -740 183 +rect -786 21 -780 171 +rect -746 21 -740 171 +rect -786 9 -740 21 +rect -350 171 -304 183 +rect -350 21 -344 171 +rect -310 21 -304 171 +rect -350 9 -304 21 +rect 86 171 132 183 +rect 86 21 92 171 +rect 126 21 132 171 +rect 86 9 132 21 +rect 522 171 568 183 +rect 522 21 528 171 +rect 562 21 568 171 +rect 522 9 568 21 +rect -568 -21 -522 -9 +rect -568 -171 -562 -21 +rect -528 -171 -522 -21 +rect -568 -183 -522 -171 +rect -132 -21 -86 -9 +rect -132 -171 -126 -21 +rect -92 -171 -86 -21 +rect -132 -183 -86 -171 +rect 304 -21 350 -9 +rect 304 -171 310 -21 +rect 344 -171 350 -21 +rect 304 -183 350 -171 +rect 740 -21 786 -9 +rect 740 -171 746 -21 +rect 780 -171 786 -21 +rect 740 -183 786 -171 +rect -920 -275 -874 -263 +rect -730 -238 -578 -232 +rect -730 -272 -718 -238 +rect -590 -272 -578 -238 +rect -730 -278 -578 -272 +rect -512 -238 -360 -232 +rect -512 -272 -500 -238 +rect -372 -272 -360 -238 +rect -512 -278 -360 -272 +rect -294 -238 -142 -232 +rect -294 -272 -282 -238 +rect -154 -272 -142 -238 +rect -294 -278 -142 -272 +rect -76 -238 76 -232 +rect -76 -272 -64 -238 +rect 64 -272 76 -238 +rect -76 -278 76 -272 +rect 142 -238 294 -232 +rect 142 -272 154 -238 +rect 282 -272 294 -238 +rect 142 -278 294 -272 +rect 360 -238 512 -232 +rect 360 -272 372 -238 +rect 500 -272 512 -238 +rect 360 -278 512 -272 +rect 578 -238 730 -232 +rect 578 -272 590 -238 +rect 718 -272 730 -238 +rect 578 -278 730 -272 +<< properties >> +string gencell sky130_fd_pr__nfet_g5v0d10v5 +string FIXED_BBOX -897 -393 897 393 +string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc +40 viadrn -40 viagate 100 viagb 0 viagr 0 viagl 70 viagt 0 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag b/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag new file mode 100644 index 0000000..eb312e6 --- /dev/null +++ b/mag/sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC.mag
@@ -0,0 +1,93 @@ +magic +tech sky130A +timestamp 1605994897 +<< pwell >> +rect -154 -229 154 229 +<< mvnmos >> +rect -40 -100 40 100 +<< mvndiff >> +rect -69 94 -40 100 +rect -69 -94 -63 94 +rect -46 -94 -40 94 +rect -69 -100 -40 -94 +rect 40 94 69 100 +rect 40 -94 46 94 +rect 63 -94 69 94 +rect 40 -100 69 -94 +<< mvndiffc >> +rect -63 -94 -46 94 +rect 46 -94 63 94 +<< mvpsubdiff >> +rect -136 205 136 211 +rect -136 188 -82 205 +rect 82 188 136 205 +rect -136 182 136 188 +rect -136 -182 -107 182 +rect 107 157 136 182 +rect 107 -157 113 157 +rect 130 -157 136 157 +rect 107 -182 136 -157 +rect -136 -188 136 -182 +rect -136 -205 -82 -188 +rect 82 -205 136 -188 +rect -136 -211 136 -205 +<< mvpsubdiffcont >> +rect -82 188 82 205 +rect 113 -157 130 157 +rect -82 -205 82 -188 +<< poly >> +rect -40 136 40 144 +rect -40 119 -32 136 +rect 32 119 40 136 +rect -40 100 40 119 +rect -40 -119 40 -100 +rect -40 -136 -32 -119 +rect 32 -136 40 -119 +rect -40 -144 40 -136 +<< polycont >> +rect -32 119 32 136 +rect -32 -136 32 -119 +<< locali >> +rect -130 188 -82 205 +rect 82 188 130 205 +rect -130 -188 -113 188 +rect 113 157 130 188 +rect -40 119 -32 136 +rect 32 119 40 136 +rect -63 94 -46 102 +rect -63 -102 -46 -94 +rect 46 94 63 102 +rect 46 -102 63 -94 +rect -40 -136 -32 -119 +rect 32 -136 40 -119 +rect 113 -188 130 -157 +rect -130 -205 -82 -188 +rect 82 -205 130 -188 +<< viali >> +rect -32 119 32 136 +rect -63 -94 -46 94 +rect 46 -94 63 94 +rect -32 -136 32 -119 +<< metal1 >> +rect -38 136 38 139 +rect -38 119 -32 136 +rect 32 119 38 136 +rect -38 116 38 119 +rect -66 94 -43 100 +rect -66 -94 -63 94 +rect -46 -94 -43 94 +rect -66 -100 -43 -94 +rect 43 94 66 100 +rect 43 -94 46 94 +rect 63 -94 66 94 +rect 43 -100 66 -94 +rect -38 -119 38 -116 +rect -38 -136 -32 -119 +rect 32 -136 38 -119 +rect -38 -139 38 -136 +<< properties >> +string gencell sky130_fd_pr__nfet_g5v0d10v5 +string FIXED_BBOX -121 -196 121 196 +string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 0 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt} full_metal 1 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag new file mode 100644 index 0000000..e0b0219 --- /dev/null +++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_3YBPVB.mag
@@ -0,0 +1,106 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606063140 +<< nwell >> +rect -338 -497 338 497 +<< mvpmos >> +rect -80 -200 80 200 +<< mvpdiff >> +rect -138 188 -80 200 +rect -138 -188 -126 188 +rect -92 -188 -80 188 +rect -138 -200 -80 -188 +rect 80 188 138 200 +rect 80 -188 92 188 +rect 126 -188 138 188 +rect 80 -200 138 -188 +<< mvpdiffc >> +rect -126 -188 -92 188 +rect 92 -188 126 188 +<< mvnsubdiff >> +rect -272 419 272 431 +rect -272 385 -164 419 +rect 164 385 272 419 +rect -272 373 272 385 +rect -272 323 -214 373 +rect -272 -323 -260 323 +rect -226 -323 -214 323 +rect 214 323 272 373 +rect -272 -373 -214 -323 +rect 214 -323 226 323 +rect 260 -323 272 323 +rect 214 -373 272 -323 +rect -272 -385 272 -373 +rect -272 -419 -164 -385 +rect 164 -419 272 -385 +rect -272 -431 272 -419 +<< mvnsubdiffcont >> +rect -164 385 164 419 +rect -260 -323 -226 323 +rect 226 -323 260 323 +rect -164 -419 164 -385 +<< poly >> +rect -80 281 80 297 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -80 200 80 247 +rect -80 -247 80 -200 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -80 -297 80 -281 +<< polycont >> +rect -64 247 64 281 +rect -64 -281 64 -247 +<< locali >> +rect -260 385 -181 419 +rect 181 385 260 419 +rect -260 323 -226 385 +rect 226 323 260 385 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -126 188 -92 204 +rect -126 -204 -92 -188 +rect 92 188 126 204 +rect 92 -204 126 -188 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -260 -385 -226 -323 +rect 226 -385 260 -323 +rect -260 -419 -164 -385 +rect 164 -419 260 -385 +<< viali >> +rect -181 385 -164 419 +rect -164 385 164 419 +rect 164 385 181 419 +rect -64 247 64 281 +rect -126 -188 -92 188 +rect 92 -188 126 188 +rect -64 -281 64 -247 +<< metal1 >> +rect -193 419 193 425 +rect -193 385 -181 419 +rect 181 385 193 419 +rect -193 379 193 385 +rect -76 281 76 287 +rect -76 247 -64 281 +rect 64 247 76 281 +rect -76 241 76 247 +rect -132 188 -86 200 +rect -132 -188 -126 188 +rect -92 -188 -86 188 +rect -132 -200 -86 -188 +rect 86 188 132 200 +rect 86 -188 92 188 +rect 126 -188 132 188 +rect 86 -200 132 -188 +rect -76 -247 76 -241 +rect -76 -281 -64 -247 +rect 64 -281 76 -247 +rect -76 -287 76 -281 +<< properties >> +string gencell sky130_fd_pr__pfet_g5v0d10v5 +string FIXED_BBOX -243 -402 243 402 +string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl 0 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag new file mode 100644 index 0000000..08a17b0 --- /dev/null +++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_YEUEBV.mag
@@ -0,0 +1,331 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606063140 +<< nwell >> +rect -992 -497 992 497 +<< mvpmos >> +rect -734 -200 -574 200 +rect -516 -200 -356 200 +rect -298 -200 -138 200 +rect -80 -200 80 200 +rect 138 -200 298 200 +rect 356 -200 516 200 +rect 574 -200 734 200 +<< mvpdiff >> +rect -792 188 -734 200 +rect -792 -188 -780 188 +rect -746 -188 -734 188 +rect -792 -200 -734 -188 +rect -574 188 -516 200 +rect -574 -188 -562 188 +rect -528 -188 -516 188 +rect -574 -200 -516 -188 +rect -356 188 -298 200 +rect -356 -188 -344 188 +rect -310 -188 -298 188 +rect -356 -200 -298 -188 +rect -138 188 -80 200 +rect -138 -188 -126 188 +rect -92 -188 -80 188 +rect -138 -200 -80 -188 +rect 80 188 138 200 +rect 80 -188 92 188 +rect 126 -188 138 188 +rect 80 -200 138 -188 +rect 298 188 356 200 +rect 298 -188 310 188 +rect 344 -188 356 188 +rect 298 -200 356 -188 +rect 516 188 574 200 +rect 516 -188 528 188 +rect 562 -188 574 188 +rect 516 -200 574 -188 +rect 734 188 792 200 +rect 734 -188 746 188 +rect 780 -188 792 188 +rect 734 -200 792 -188 +<< mvpdiffc >> +rect -780 -188 -746 188 +rect -562 -188 -528 188 +rect -344 -188 -310 188 +rect -126 -188 -92 188 +rect 92 -188 126 188 +rect 310 -188 344 188 +rect 528 -188 562 188 +rect 746 -188 780 188 +<< mvnsubdiff >> +rect -926 419 926 431 +rect -926 385 -818 419 +rect 818 385 926 419 +rect -926 373 926 385 +rect -926 323 -868 373 +rect -926 -323 -914 323 +rect -880 -323 -868 323 +rect 868 323 926 373 +rect -926 -373 -868 -323 +rect 868 -323 880 323 +rect 914 -323 926 323 +rect 868 -373 926 -323 +rect -926 -385 926 -373 +rect -926 -419 -818 -385 +rect 818 -419 926 -385 +rect -926 -431 926 -419 +<< mvnsubdiffcont >> +rect -818 385 818 419 +rect -914 -323 -880 323 +rect 880 -323 914 323 +rect -818 -419 818 -385 +<< poly >> +rect -734 281 -574 297 +rect -734 247 -718 281 +rect -590 247 -574 281 +rect -734 200 -574 247 +rect -516 281 -356 297 +rect -516 247 -500 281 +rect -372 247 -356 281 +rect -516 200 -356 247 +rect -298 281 -138 297 +rect -298 247 -282 281 +rect -154 247 -138 281 +rect -298 200 -138 247 +rect -80 281 80 297 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -80 200 80 247 +rect 138 281 298 297 +rect 138 247 154 281 +rect 282 247 298 281 +rect 138 200 298 247 +rect 356 281 516 297 +rect 356 247 372 281 +rect 500 247 516 281 +rect 356 200 516 247 +rect 574 281 734 297 +rect 574 247 590 281 +rect 718 247 734 281 +rect 574 200 734 247 +rect -734 -247 -574 -200 +rect -734 -281 -718 -247 +rect -590 -281 -574 -247 +rect -734 -297 -574 -281 +rect -516 -247 -356 -200 +rect -516 -281 -500 -247 +rect -372 -281 -356 -247 +rect -516 -297 -356 -281 +rect -298 -247 -138 -200 +rect -298 -281 -282 -247 +rect -154 -281 -138 -247 +rect -298 -297 -138 -281 +rect -80 -247 80 -200 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -80 -297 80 -281 +rect 138 -247 298 -200 +rect 138 -281 154 -247 +rect 282 -281 298 -247 +rect 138 -297 298 -281 +rect 356 -247 516 -200 +rect 356 -281 372 -247 +rect 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512 281 +rect 360 241 512 247 +rect 578 281 730 287 +rect 578 247 590 281 +rect 718 247 730 281 +rect 578 241 730 247 +rect -920 26 -874 38 +rect -786 171 -740 183 +rect -786 21 -780 171 +rect -746 21 -740 171 +rect -786 9 -740 21 +rect -350 171 -304 183 +rect -350 21 -344 171 +rect -310 21 -304 171 +rect -350 9 -304 21 +rect 86 171 132 183 +rect 86 21 92 171 +rect 126 21 132 171 +rect 86 9 132 21 +rect 522 171 568 183 +rect 522 21 528 171 +rect 562 21 568 171 +rect 522 9 568 21 +rect -568 -21 -522 -9 +rect -568 -171 -562 -21 +rect -528 -171 -522 -21 +rect -568 -183 -522 -171 +rect -132 -21 -86 -9 +rect -132 -171 -126 -21 +rect -92 -171 -86 -21 +rect -132 -183 -86 -171 +rect 304 -21 350 -9 +rect 304 -171 310 -21 +rect 344 -171 350 -21 +rect 304 -183 350 -171 +rect 740 -21 786 -9 +rect 740 -171 746 -21 +rect 780 -171 786 -21 +rect 740 -183 786 -171 +rect -730 -247 -578 -241 +rect -730 -281 -718 -247 +rect -590 -281 -578 -247 +rect -730 -287 -578 -281 +rect -512 -247 -360 -241 +rect -512 -281 -500 -247 +rect -372 -281 -360 -247 +rect -512 -287 -360 -281 +rect -294 -247 -142 -241 +rect -294 -281 -282 -247 +rect -154 -281 -142 -247 +rect -294 -287 -142 -281 +rect -76 -247 76 -241 +rect -76 -281 -64 -247 +rect 64 -281 76 -247 +rect -76 -287 76 -281 +rect 142 -247 294 -241 +rect 142 -281 154 -247 +rect 282 -281 294 -247 +rect 142 -287 294 -281 +rect 360 -247 512 -241 +rect 360 -281 372 -247 +rect 500 -281 512 -247 +rect 360 -287 512 -281 +rect 578 -247 730 -241 +rect 578 -281 590 -247 +rect 718 -281 730 -247 +rect 578 -287 730 -281 +<< properties >> +string gencell sky130_fd_pr__pfet_g5v0d10v5 +string FIXED_BBOX -897 -402 897 402 +string parameters w 2.00 l 0.80 m 1 nf 7 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag new file mode 100644 index 0000000..eb421da --- /dev/null +++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPBG.mag
@@ -0,0 +1,114 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606063140 +<< error_p >> +rect -221 351 -220 397 +rect -193 379 -192 419 +<< nwell >> +rect -338 -497 338 497 +<< mvpmos >> +rect -80 -200 80 200 +<< mvpdiff >> +rect -138 188 -80 200 +rect -138 -188 -126 188 +rect -92 -188 -80 188 +rect -138 -200 -80 -188 +rect 80 188 138 200 +rect 80 -188 92 188 +rect 126 -188 138 188 +rect 80 -200 138 -188 +<< mvpdiffc >> +rect -126 -188 -92 188 +rect 92 -188 126 188 +<< mvnsubdiff >> +rect -272 419 272 431 +rect -272 385 -164 419 +rect 164 385 272 419 +rect -272 373 272 385 +rect -272 323 -214 373 +rect -272 -323 -260 323 +rect -226 -323 -214 323 +rect 214 323 272 373 +rect -272 -373 -214 -323 +rect 214 -323 226 323 +rect 260 -323 272 323 +rect 214 -373 272 -323 +rect -272 -385 272 -373 +rect -272 -419 -164 -385 +rect 164 -419 272 -385 +rect -272 -431 272 -419 +<< mvnsubdiffcont >> +rect -164 385 164 419 +rect -260 -323 -226 323 +rect 226 -323 260 323 +rect -164 -419 164 -385 +<< poly >> +rect -80 281 80 297 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -80 200 80 247 +rect -80 -247 80 -200 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -80 -297 80 -281 +<< polycont >> +rect -64 247 64 281 +rect -64 -281 64 -247 +<< locali >> +rect -260 385 -181 419 +rect 181 385 260 419 +rect 226 323 260 385 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -126 188 -92 204 +rect -126 -204 -92 -188 +rect 92 188 126 204 +rect 92 -204 126 -188 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -260 -385 -226 -323 +rect 226 -385 260 -323 +rect -260 -419 -164 -385 +rect 164 -419 260 -385 +<< viali >> +rect -181 385 -164 419 +rect -164 385 164 419 +rect 164 385 181 419 +rect -260 323 -226 385 +rect -260 0 -226 323 +rect -64 247 64 281 +rect -126 -188 -92 188 +rect 92 -188 126 188 +rect -64 -281 64 -247 +<< metal1 >> +rect -193 419 193 425 +rect -266 385 -220 397 +rect -266 0 -260 385 +rect -226 0 -220 385 +rect -193 385 -181 419 +rect 181 385 193 419 +rect -193 379 193 385 +rect -76 281 76 287 +rect -76 247 -64 281 +rect 64 247 76 281 +rect -76 241 76 247 +rect -266 -12 -220 0 +rect -132 188 -86 200 +rect -132 -188 -126 188 +rect -92 -188 -86 188 +rect -132 -200 -86 -188 +rect 86 188 132 200 +rect 86 -188 92 188 +rect 126 -188 132 188 +rect 86 -200 132 -188 +rect -76 -247 76 -241 +rect -76 -281 -64 -247 +rect 64 -281 76 -247 +rect -76 -287 76 -281 +<< properties >> +string gencell sky130_fd_pr__pfet_g5v0d10v5 +string FIXED_BBOX -243 -402 243 402 +string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag new file mode 100644 index 0000000..19fe898 --- /dev/null +++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_YUHPXE.mag
@@ -0,0 +1,114 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606063140 +<< error_p >> +rect -221 351 -220 397 +rect -193 379 -192 419 +<< nwell >> +rect -338 -497 338 497 +<< mvpmos >> +rect -80 -200 80 200 +<< mvpdiff >> +rect -138 188 -80 200 +rect -138 -188 -126 188 +rect -92 -188 -80 188 +rect -138 -200 -80 -188 +rect 80 188 138 200 +rect 80 -188 92 188 +rect 126 -188 138 188 +rect 80 -200 138 -188 +<< mvpdiffc >> +rect -126 -188 -92 188 +rect 92 -188 126 188 +<< mvnsubdiff >> +rect -272 419 272 431 +rect -272 385 -164 419 +rect 164 385 272 419 +rect -272 373 272 385 +rect -272 323 -214 373 +rect -272 -323 -260 323 +rect -226 -323 -214 323 +rect 214 323 272 373 +rect -272 -373 -214 -323 +rect 214 -323 226 323 +rect 260 -323 272 323 +rect 214 -373 272 -323 +rect -272 -385 272 -373 +rect -272 -419 -164 -385 +rect 164 -419 272 -385 +rect -272 -431 272 -419 +<< mvnsubdiffcont >> +rect -164 385 164 419 +rect -260 -323 -226 323 +rect 226 -323 260 323 +rect -164 -419 164 -385 +<< poly >> +rect -80 281 80 297 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -80 200 80 247 +rect -80 -247 80 -200 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -80 -297 80 -281 +<< polycont >> +rect -64 247 64 281 +rect -64 -281 64 -247 +<< locali >> +rect -260 385 -181 419 +rect 181 385 260 419 +rect 226 323 260 385 +rect -80 247 -64 281 +rect 64 247 80 281 +rect -126 188 -92 204 +rect -126 -204 -92 -188 +rect 92 188 126 204 +rect 92 -204 126 -188 +rect -80 -281 -64 -247 +rect 64 -281 80 -247 +rect -260 -385 -226 -323 +rect 226 -385 260 -323 +rect -260 -419 -164 -385 +rect 164 -419 260 -385 +<< viali >> +rect -181 385 -164 419 +rect -164 385 164 419 +rect 164 385 181 419 +rect -260 323 -226 385 +rect -260 38 -226 323 +rect -64 247 64 281 +rect -126 -188 -92 188 +rect 92 -188 126 188 +rect -64 -281 64 -247 +<< metal1 >> +rect -193 419 193 425 +rect -266 385 -220 397 +rect -266 38 -260 385 +rect -226 38 -220 385 +rect -193 385 -181 419 +rect 181 385 193 419 +rect -193 379 193 385 +rect -76 281 76 287 +rect -76 247 -64 281 +rect 64 247 76 281 +rect -76 241 76 247 +rect -266 26 -220 38 +rect -132 188 -86 200 +rect -132 -188 -126 188 +rect -92 -188 -86 188 +rect -132 -200 -86 -188 +rect 86 188 132 200 +rect 86 -188 92 188 +rect 126 -188 132 188 +rect 86 -200 132 -188 +rect -76 -247 76 -241 +rect -76 -281 -64 -247 +rect 64 -281 76 -247 +rect -76 -287 76 -281 +<< properties >> +string gencell sky130_fd_pr__pfet_g5v0d10v5 +string FIXED_BBOX -243 -402 243 402 +string parameters w 2.00 l 0.80 m 1 nf 1 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -45 viagr 0 viagt 80 viagb 0 viagate 100 viadrn 100 viasrc 100 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag b/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag new file mode 100644 index 0000000..b8eb64f --- /dev/null +++ b/mag/sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ.mag
@@ -0,0 +1,368 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606063140 +<< nwell >> +rect -1101 -497 1101 497 +<< mvpmos >> +rect -843 -200 -683 200 +rect -625 -200 -465 200 +rect -407 -200 -247 200 +rect -189 -200 -29 200 +rect 29 -200 189 200 +rect 247 -200 407 200 +rect 465 -200 625 200 +rect 683 -200 843 200 +<< mvpdiff >> +rect -901 188 -843 200 +rect -901 -188 -889 188 +rect -855 -188 -843 188 +rect -901 -200 -843 -188 +rect -683 188 -625 200 +rect -683 -188 -671 188 +rect -637 -188 -625 188 +rect -683 -200 -625 -188 +rect -465 188 -407 200 +rect -465 -188 -453 188 +rect -419 -188 -407 188 +rect -465 -200 -407 -188 +rect -247 188 -189 200 +rect -247 -188 -235 188 +rect -201 -188 -189 188 +rect -247 -200 -189 -188 +rect -29 188 29 200 +rect -29 -188 -17 188 +rect 17 -188 29 188 +rect -29 -200 29 -188 +rect 189 188 247 200 +rect 189 -188 201 188 +rect 235 -188 247 188 +rect 189 -200 247 -188 +rect 407 188 465 200 +rect 407 -188 419 188 +rect 453 -188 465 188 +rect 407 -200 465 -188 +rect 625 188 683 200 +rect 625 -188 637 188 +rect 671 -188 683 188 +rect 625 -200 683 -188 +rect 843 188 901 200 +rect 843 -188 855 188 +rect 889 -188 901 188 +rect 843 -200 901 -188 +<< mvpdiffc >> +rect -889 -188 -855 188 +rect -671 -188 -637 188 +rect -453 -188 -419 188 +rect -235 -188 -201 188 +rect -17 -188 17 188 +rect 201 -188 235 188 +rect 419 -188 453 188 +rect 637 -188 671 188 +rect 855 -188 889 188 +<< mvnsubdiff >> +rect -1035 419 1035 431 +rect -1035 385 -927 419 +rect 927 385 1035 419 +rect -1035 373 1035 385 +rect -1035 323 -977 373 +rect -1035 -323 -1023 323 +rect -989 -323 -977 323 +rect 977 323 1035 373 +rect -1035 -373 -977 -323 +rect 977 -323 989 323 +rect 1023 -323 1035 323 +rect 977 -373 1035 -323 +rect -1035 -385 1035 -373 +rect -1035 -419 -927 -385 +rect 927 -419 1035 -385 +rect -1035 -431 1035 -419 +<< mvnsubdiffcont >> +rect -927 385 927 419 +rect -1023 -323 -989 323 +rect 989 -323 1023 323 +rect -927 -419 927 -385 +<< poly >> +rect -843 281 -683 297 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397 +rect -1029 0 -1023 385 +rect -989 0 -983 385 +rect -902 385 -890 419 +rect 890 385 902 419 +rect -902 379 902 385 +rect -839 281 -687 287 +rect -839 247 -827 281 +rect -699 247 -687 281 +rect -839 241 -687 247 +rect -621 281 -469 287 +rect -621 247 -609 281 +rect -481 247 -469 281 +rect -621 241 -469 247 +rect -403 281 -251 287 +rect -403 247 -391 281 +rect -263 247 -251 281 +rect -403 241 -251 247 +rect -185 281 -33 287 +rect -185 247 -173 281 +rect -45 247 -33 281 +rect -185 241 -33 247 +rect 33 281 185 287 +rect 33 247 45 281 +rect 173 247 185 281 +rect 33 241 185 247 +rect 251 281 403 287 +rect 251 247 263 281 +rect 391 247 403 281 +rect 251 241 403 247 +rect 469 281 621 287 +rect 469 247 481 281 +rect 609 247 621 281 +rect 469 241 621 247 +rect 687 281 839 287 +rect 687 247 699 281 +rect 827 247 839 281 +rect 687 241 839 247 +rect -895 171 -849 183 +rect -895 21 -889 171 +rect -855 21 -849 171 +rect -895 9 -849 21 +rect -459 171 -413 183 +rect -459 21 -453 171 +rect -419 21 -413 171 +rect -459 9 -413 21 +rect -23 171 23 183 +rect -23 21 -17 171 +rect 17 21 23 171 +rect -23 9 23 21 +rect 413 171 459 183 +rect 413 21 419 171 +rect 453 21 459 171 +rect 413 9 459 21 +rect 849 171 895 183 +rect 849 21 855 171 +rect 889 21 895 171 +rect 849 9 895 21 +rect -1029 -12 -983 0 +rect -677 -21 -631 -9 +rect -677 -171 -671 -21 +rect -637 -171 -631 -21 +rect -677 -183 -631 -171 +rect -241 -21 -195 -9 +rect -241 -171 -235 -21 +rect -201 -171 -195 -21 +rect -241 -183 -195 -171 +rect 195 -21 241 -9 +rect 195 -171 201 -21 +rect 235 -171 241 -21 +rect 195 -183 241 -171 +rect 631 -21 677 -9 +rect 631 -171 637 -21 +rect 671 -171 677 -21 +rect 631 -183 677 -171 +rect -839 -247 -687 -241 +rect -839 -281 -827 -247 +rect -699 -281 -687 -247 +rect -839 -287 -687 -281 +rect -621 -247 -469 -241 +rect -621 -281 -609 -247 +rect -481 -281 -469 -247 +rect -621 -287 -469 -281 +rect -403 -247 -251 -241 +rect -403 -281 -391 -247 +rect -263 -281 -251 -247 +rect -403 -287 -251 -281 +rect -185 -247 -33 -241 +rect -185 -281 -173 -247 +rect -45 -281 -33 -247 +rect -185 -287 -33 -281 +rect 33 -247 185 -241 +rect 33 -281 45 -247 +rect 173 -281 185 -247 +rect 33 -287 185 -281 +rect 251 -247 403 -241 +rect 251 -281 263 -247 +rect 391 -281 403 -247 +rect 251 -287 403 -281 +rect 469 -247 621 -241 +rect 469 -281 481 -247 +rect 609 -281 621 -247 +rect 469 -287 621 -281 +rect 687 -247 839 -241 +rect 687 -281 699 -247 +rect 827 -281 839 -247 +rect 687 -287 839 -281 +<< properties >> +string gencell sky130_fd_pr__pfet_g5v0d10v5 +string FIXED_BBOX -1006 -402 1006 402 +string parameters w 2.00 l 0.80 m 1 nf 8 diffcov 100 polycov 100 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 100 rlcov 100 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.50 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 1 viagl -50 viagr 0 viagt 90 viagb 0 viagate 100 viadrn -40 viasrc +40 +string library sky130 +<< end >>
diff --git a/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag b/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag new file mode 100644 index 0000000..5bd3cec --- /dev/null +++ b/mag/sky130_fd_pr__res_xhigh_po_0p69_S5N9F3.mag
@@ -0,0 +1,167 @@ +magic +tech sky130A +magscale 1 2 +timestamp 1606074388 +<< pwell >> +rect -5446 -3098 5446 3098 +<< psubdiff >> +rect -5410 3028 -5314 3062 +rect 5314 3028 5410 3062 +rect -5410 2966 -5376 3028 +rect 5376 2966 5410 3028 +rect -5410 -3028 -5376 -2966 +rect 5376 -3028 5410 -2966 +rect -5410 -3062 -5314 -3028 +rect 5314 -3062 5410 -3028 +<< psubdiffcont >> +rect -5314 3028 5314 3062 +rect -5410 -2966 -5376 2966 +rect 5376 -2966 5410 2966 +rect -5314 -3062 5314 -3028 +<< xpolycontact >> +rect -5280 2500 -5142 2932 +rect -5280 -2932 -5142 -2500 +rect -4894 2500 -4756 2932 +rect -4894 -2932 -4756 -2500 +rect -4508 2500 -4370 2932 +rect -4508 -2932 -4370 -2500 +rect -4122 2500 -3984 2932 +rect -4122 -2932 -3984 -2500 +rect -3736 2500 -3598 2932 +rect -3736 -2932 -3598 -2500 +rect -3350 2500 -3212 2932 +rect -3350 -2932 -3212 -2500 +rect -2964 2500 -2826 2932 +rect -2964 -2932 -2826 -2500 +rect -2578 2500 -2440 2932 +rect -2578 -2932 -2440 -2500 +rect -2192 2500 -2054 2932 +rect -2192 -2932 -2054 -2500 +rect -1806 2500 -1668 2932 +rect -1806 -2932 -1668 -2500 +rect -1420 2500 -1282 2932 +rect -1420 -2932 -1282 -2500 +rect -1034 2500 -896 2932 +rect -1034 -2932 -896 -2500 +rect -648 2500 -510 2932 +rect -648 -2932 -510 -2500 +rect -262 2500 -124 2932 +rect -262 -2932 -124 -2500 +rect 124 2500 262 2932 +rect 124 -2932 262 -2500 +rect 510 2500 648 2932 +rect 510 -2932 648 -2500 +rect 896 2500 1034 2932 +rect 896 -2932 1034 -2500 +rect 1282 2500 1420 2932 +rect 1282 -2932 1420 -2500 +rect 1668 2500 1806 2932 +rect 1668 -2932 1806 -2500 +rect 2054 2500 2192 2932 +rect 2054 -2932 2192 -2500 +rect 2440 2500 2578 2932 +rect 2440 -2932 2578 -2500 +rect 2826 2500 2964 2932 +rect 2826 -2932 2964 -2500 +rect 3212 2500 3350 2932 +rect 3212 -2932 3350 -2500 +rect 3598 2500 3736 2932 +rect 3598 -2932 3736 -2500 +rect 3984 2500 4122 2932 +rect 3984 -2932 4122 -2500 +rect 4370 2500 4508 2932 +rect 4370 -2932 4508 -2500 +rect 4756 2500 4894 2932 +rect 4756 -2932 4894 -2500 +rect 5142 2500 5280 2932 +rect 5142 -2932 5280 -2500 +<< xpolyres >> +rect -5280 -2500 -5142 2500 +rect -4894 -2500 -4756 2500 +rect -4508 -2500 -4370 2500 +rect -4122 -2500 -3984 2500 +rect -3736 -2500 -3598 2500 +rect -3350 -2500 -3212 2500 +rect -2964 -2500 -2826 2500 +rect -2578 -2500 -2440 2500 +rect -2192 -2500 -2054 2500 +rect -1806 -2500 -1668 2500 +rect -1420 -2500 -1282 2500 +rect -1034 -2500 -896 2500 +rect -648 -2500 -510 2500 +rect -262 -2500 -124 2500 +rect 124 -2500 262 2500 +rect 510 -2500 648 2500 +rect 896 -2500 1034 2500 +rect 1282 -2500 1420 2500 +rect 1668 -2500 1806 2500 +rect 2054 -2500 2192 2500 +rect 2440 -2500 2578 2500 +rect 2826 -2500 2964 2500 +rect 3212 -2500 3350 2500 +rect 3598 -2500 3736 2500 +rect 3984 -2500 4122 2500 +rect 4370 -2500 4508 2500 +rect 4756 -2500 4894 2500 +rect 5142 -2500 5280 2500 +<< locali >> +rect -5410 3028 -5314 3062 +rect 5314 3028 5410 3062 +rect -5410 2966 -5376 3028 +rect 5376 2966 5410 3028 +rect -5410 -3028 -5376 -2966 +rect 5376 -3028 5410 -2966 +rect -5410 -3062 -5314 -3028 +rect 5314 -3062 5410 -3028 +<< viali >> +rect -5410 -2725 -5376 2725 +rect 5376 -2725 5410 2725 +rect -4838 -3062 4838 -3028 +<< metal1 >> +rect -5416 2725 -5370 2737 +rect -5416 -2725 -5410 2725 +rect -5376 -2725 -5370 2725 +rect -5416 -2737 -5370 -2725 +rect 5370 2725 5416 2737 +rect 5370 -2725 5376 2725 +rect 5410 -2725 5416 2725 +rect 5370 -2737 5416 -2725 +rect -4850 -3028 4850 -3022 +rect -4850 -3062 -4838 -3028 +rect 4838 -3062 4850 -3028 +rect -4850 -3068 4850 -3062 +<< res0p69 >> +rect -5282 -2502 -5140 2502 +rect -4896 -2502 -4754 2502 +rect -4510 -2502 -4368 2502 +rect -4124 -2502 -3982 2502 +rect -3738 -2502 -3596 2502 +rect -3352 -2502 -3210 2502 +rect -2966 -2502 -2824 2502 +rect -2580 -2502 -2438 2502 +rect -2194 -2502 -2052 2502 +rect -1808 -2502 -1666 2502 +rect -1422 -2502 -1280 2502 +rect -1036 -2502 -894 2502 +rect -650 -2502 -508 2502 +rect -264 -2502 -122 2502 +rect 122 -2502 264 2502 +rect 508 -2502 650 2502 +rect 894 -2502 1036 2502 +rect 1280 -2502 1422 2502 +rect 1666 -2502 1808 2502 +rect 2052 -2502 2194 2502 +rect 2438 -2502 2580 2502 +rect 2824 -2502 2966 2502 +rect 3210 -2502 3352 2502 +rect 3596 -2502 3738 2502 +rect 3982 -2502 4124 2502 +rect 4368 -2502 4510 2502 +rect 4754 -2502 4896 2502 +rect 5140 -2502 5282 2502 +<< properties >> +string gencell sky130_fd_pr__res_xhigh_po_0p69 +string FIXED_BBOX -5393 -3045 5393 3045 +string parameters w 0.69 l 25.0 m 1 nx 28 wmin 0.690 lmin 0.50 rho 2000 val 72.811k dummy 0 dw 0.0 term 120 sterm 0.0 caplen 0 wmax 0.690 guard 1 glc 1 grc 1 gtc 1 gbc 1 compatible {sky130_fd_pr__res_xhigh_po_0p35 sky130_fd_pr__res_xhigh_po_0p69 sky130_fd_pr__res_xhigh_po_1p41 sky130_fd_pr__res_xhigh_po_2p85 sky130_fd_pr__res_xhigh_po_5p73} full_metal 1 vias 0 viagb 90 viagt 0 viagl 90 viagr 90 +string library sky130 +<< end >>
diff --git a/ngspice/digital_pll/digital_pll.spice b/ngspice/digital_pll/digital_pll.spice new file mode 100644 index 0000000..a755d9a --- /dev/null +++ b/ngspice/digital_pll/digital_pll.spice
@@ -0,0 +1,28 @@ +*--------------------------------------------------------------------------- +* All-digital Frequency-locked loop +*--------------------------------------------------------------------------- +* To make this simulatable, the circuit is broken into the ring oscillator +* and controller, separately, with the controller converted into an xspice +* model. +* +* For simplicity, the DCO mode has been removed, so no external trim with +* multiplexer. Also no multiplexer on the internal reset. +*--------------------------------------------------------------------------- + +.include "digital_pll_controller.xspice" +.include "ring_osc2x13.spice" + +.subckt digital_pll vdd vss reset osc clockp1 clockp0 div4 div3 div2 div1 div0 + +X0 vdd vss clockp0 div0 div1 div2 div3 div4 osc reset trim0 trim1 trim2 trim3 ++ trim4 trim5 trim6 trim7 trim8 trim9 trim10 trim11 trim12 trim13 trim14 ++ trim15 trim16 trim17 trim18 trim19 trim20 trim21 trim22 trim23 trim24 ++ trim25 digital_pll_controller + +X1 vdd vss clockp0 clockp1 reset trim0 trim1 trim2 trim3 trim4 trim5 trim6 trim7 ++ trim8 trim9 trim10 trim11 trim12 trim13 trim14 trim15 trim16 trim17 trim18 ++ trim19 trim20 trim21 trim22 trim23 trim24 trim25 ring_osc2x13 + +.ends + +
diff --git a/ngspice/digital_pll/digital_pll_controller.xspice b/ngspice/digital_pll/digital_pll_controller.xspice new file mode 100644 index 0000000..2709728 --- /dev/null +++ b/ngspice/digital_pll/digital_pll_controller.xspice
@@ -0,0 +1,496 @@ +* XSpice netlist created from SPICE and liberty sources by spi2xspice.py +*SPICE netlist created from verilog structural netlist module digital_pll_controller by vlog2Spice (qflow) +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +* SPDX-License-Identifier: Apache-2.0 +******* EOF +** End of included library /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice +.subckt digital_pll_controller a_VPB a_VGND a_clock a_div_0_ a_div_1_ a_div_2_ a_div_3_ a_div_4_ a_osc a_reset a_trim_0_ a_trim_1_ a_trim_2_ a_trim_3_ a_trim_4_ a_trim_5_ a_trim_6_ a_trim_7_ a_trim_8_ a_trim_9_ a_trim_10_ a_trim_11_ a_trim_12_ a_trim_13_ a_trim_14_ a_trim_15_ a_trim_16_ a_trim_17_ a_trim_18_ a_trim_19_ a_trim_20_ a_trim_21_ a_trim_22_ a_trim_23_ a_trim_24_ a_trim_25_ +Asky130_fd_sc_hd__buf_1_insert11 [_64_] _64__bF$buf0 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert10 [_64_] _64__bF$buf1 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert9 [_64_] _64__bF$buf2 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert8 [_64_] _64__bF$buf3 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert7 [_4_] _4__bF$buf0 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert6 [_4_] _4__bF$buf1 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert5 [_4_] _4__bF$buf2 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__buf_1_insert4 [_4_] _4__bF$buf3 d_lut_sky130_fd_sc_hd__buf_1 +Asky130_fd_sc_hd__clkbuf_1_insert3 [clock] clock_bF$buf0 d_lut_sky130_fd_sc_hd__clkbuf_1 +Asky130_fd_sc_hd__clkbuf_1_insert2 [clock] clock_bF$buf1 d_lut_sky130_fd_sc_hd__clkbuf_1 +Asky130_fd_sc_hd__clkbuf_1_insert1 [clock] clock_bF$buf2 d_lut_sky130_fd_sc_hd__clkbuf_1 +Asky130_fd_sc_hd__clkbuf_1_insert0 [clock] clock_bF$buf3 d_lut_sky130_fd_sc_hd__clkbuf_1 +A_218_ [tint_1_ tint_0_] _194_ d_lut_sky130_fd_sc_hd__nor2_1 +A_219_ [tint_3_ tint_2_] _195_ d_lut_sky130_fd_sc_hd__nor2_1 +A_220_ [_194_ _195_] _196_ d_lut_sky130_fd_sc_hd__nand2_1 +A_221_ [tint_4_ _196_] _197_ d_lut_sky130_fd_sc_hd__nor2_1 +A_222_ [_197_] _217__0_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_223_ [tval_0_] _198_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_224_ [oscbuf_1_ oscbuf_2_] _199_ d_lut_sky130_fd_sc_hd__nor2_1 +A_225_ [oscbuf_1_ oscbuf_2_] _200_ d_lut_sky130_fd_sc_hd__nand2_1 +A_226_ [_200_] _201_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_227_ [_199_ _201_] _202_ d_lut_sky130_fd_sc_hd__or2_2 +A_228_ [_202_] _203_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_229_ [_203_ prep_0_] _204_ d_lut_sky130_fd_sc_hd__nand2_1 +A_230_ [prep_1_ prep_2_] _205_ d_lut_sky130_fd_sc_hd__nand2_1 +A_231_ [_205_ _204_] _206_ d_lut_sky130_fd_sc_hd__nor2_1 +A_232_ [count1_4_] _207_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_233_ [count0_4_] _208_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_234_ [_207_ _208_] _209_ d_lut_sky130_fd_sc_hd__nor2_1 +A_235_ [count1_4_ count0_4_] _210_ d_lut_sky130_fd_sc_hd__nor2_1 +A_236_ [_210_ _209_] _211_ d_lut_sky130_fd_sc_hd__or2_2 +A_237_ [count1_3_ count0_3_] _212_ d_lut_sky130_fd_sc_hd__and2_2 +A_238_ [count1_3_ count0_3_] _213_ d_lut_sky130_fd_sc_hd__nor2_1 +A_239_ [_213_] _214_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_240_ [count1_2_ count0_2_] _215_ d_lut_sky130_fd_sc_hd__and2_2 +A_241_ [_214_ _215_ _212_] _216_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_242_ [count1_1_ count0_1_] _5_ d_lut_sky130_fd_sc_hd__nand2_1 +A_243_ [count1_0_ count0_0_] _6_ d_lut_sky130_fd_sc_hd__nand2_1 +A_244_ [count1_1_ count0_1_] _7_ d_lut_sky130_fd_sc_hd__nor2_1 +A_245_ [_6_ _7_ _5_] _8_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_246_ [count1_2_ count0_2_] _9_ d_lut_sky130_fd_sc_hd__nor2_1 +A_247_ [_9_ _215_] _10_ d_lut_sky130_fd_sc_hd__nor2_1 +A_248_ [_213_ _212_] _11_ d_lut_sky130_fd_sc_hd__nor2_1 +A_249_ [_10_ _11_ _8_] _12_ d_lut_sky130_fd_sc_hd__nand3_1 +A_250_ [_12_ _216_ _211_] _13_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_251_ [_209_ _210_ _216_ _12_] _14_ d_lut_sky130_fd_sc_hd__o211a_1 +A_252_ [_14_ _13_ div_4_] _15_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_253_ [div_4_] _16_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_254_ [_211_ _12_ _216_] _17_ d_lut_sky130_fd_sc_hd__nand3_1 +A_255_ [_17_ _16_ _209_] _18_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_256_ [_15_ _18_] _19_ d_lut_sky130_fd_sc_hd__nand2_1 +A_257_ [div_3_] _20_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_258_ [_215_] _21_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_259_ [_10_ _8_] _22_ d_lut_sky130_fd_sc_hd__nand2_1 +A_260_ [_212_ _213_ _21_ _22_] _23_ d_lut_sky130_fd_sc_hd__o211ai_1 +A_261_ [_6_ _7_ _5_] _24_ d_lut_sky130_fd_sc_hd__o21a_1 +A_262_ [_9_ _24_ _215_] _25_ d_lut_sky130_fd_sc_hd__o21bai_1 +A_263_ [_25_ _11_] _26_ d_lut_sky130_fd_sc_hd__nand2_1 +A_264_ [_26_ _20_ _23_] _27_ d_lut_sky130_fd_sc_hd__nand3_1 +A_265_ [div_2_ _8_ _10_] _28_ d_lut_sky130_fd_sc_hd__xnor3_4 +A_266_ [_22_ _21_ _11_] _29_ d_lut_sky130_fd_sc_hd__nand3_1 +A_267_ [_21_ _22_ _212_ _213_] _30_ d_lut_sky130_fd_sc_hd__o2bb2ai_1 +A_268_ [_30_ div_3_ _29_] _31_ d_lut_sky130_fd_sc_hd__nand3_1 +A_269_ [div_0_] _32_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_270_ [count1_0_ count0_0_] _33_ d_lut_sky130_fd_sc_hd__xor2_1 +A_271_ [_33_ _32_] _34_ d_lut_sky130_fd_sc_hd__and2_2 +A_272_ [div_1_] _35_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_273_ [count1_1_ count0_1_] _36_ d_lut_sky130_fd_sc_hd__or2_2 +A_274_ [_36_ _5_] _37_ d_lut_sky130_fd_sc_hd__nand2_1 +A_275_ [_35_ _6_ _37_] _38_ d_lut_sky130_fd_sc_hd__xnor3_4 +A_276_ [_32_ _33_] _39_ d_lut_sky130_fd_sc_hd__nor2_1 +A_277_ [_34_ _39_ _38_] _40_ d_lut_sky130_fd_sc_hd__nor3_1 +A_278_ [_40_ _27_ _28_ _31_] _41_ d_lut_sky130_fd_sc_hd__nand4_1 +A_279_ [_41_ _19_] _42_ d_lut_sky130_fd_sc_hd__or2_2 +A_280_ [_36_ count1_0_ count0_0_ _5_] _43_ d_lut_sky130_fd_sc_hd__nand4_1 +A_281_ [count1_1_ count0_1_] _44_ d_lut_sky130_fd_sc_hd__and2_2 +A_282_ [_7_ _44_ _6_] _45_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_283_ [_45_ _43_ _35_] _46_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_284_ [_45_ _43_ _35_] _47_ d_lut_sky130_fd_sc_hd__nand3_1 +A_285_ [_33_ _32_] _48_ d_lut_sky130_fd_sc_hd__nand2_1 +A_286_ [_47_ _48_ _46_] _49_ d_lut_sky130_fd_sc_hd__a21o_2 +A_287_ [_27_ _31_ _28_ _49_] _50_ d_lut_sky130_fd_sc_hd__nand4_1 +A_288_ [_215_ _9_ _24_] _51_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_289_ [_51_ _22_ div_2_] _52_ d_lut_sky130_fd_sc_hd__a21boi_0 +A_290_ [_27_ _52_] _53_ d_lut_sky130_fd_sc_hd__nand2_1 +A_291_ [_50_ _31_ _53_ _19_] _54_ d_lut_sky130_fd_sc_hd__a31oi_1 +A_292_ [_12_ div_4_ _210_ _216_] _55_ d_lut_sky130_fd_sc_hd__nand4_1 +A_293_ [_55_] _56_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_294_ [tval_0_ tval_1_] _57_ d_lut_sky130_fd_sc_hd__nor2_1 +A_295_ [_197_ _57_] _58_ d_lut_sky130_fd_sc_hd__nand2_1 +A_296_ [_58_] _59_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_297_ [tval_0_ _59_ _56_ _54_ _42_] _60_ d_lut_sky130_fd_sc_hd__o221ai_1 +A_298_ [_15_ _18_] _61_ d_lut_sky130_fd_sc_hd__and2_2 +A_299_ [_50_ _31_ _53_] _62_ d_lut_sky130_fd_sc_hd__nand3_1 +A_300_ [_62_ _61_] _63_ d_lut_sky130_fd_sc_hd__nand2_1 +A_301_ [tint_4_] _64_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_302_ [tval_0_ tval_1_] _65_ d_lut_sky130_fd_sc_hd__nand2_1 +A_303_ [tint_1_ tint_0_] _66_ d_lut_sky130_fd_sc_hd__nand2_1 +A_304_ [_65_ _66_] _67_ d_lut_sky130_fd_sc_hd__nor2_1 +A_305_ [_67_ tint_3_ tint_2_] _68_ d_lut_sky130_fd_sc_hd__nand3_1 +A_306_ [_64__bF$buf3 _68_] _69_ d_lut_sky130_fd_sc_hd__nor2_1 +A_307_ [_69_] _70_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_308_ [_63_ tval_0_ _55_ _70_] _71_ d_lut_sky130_fd_sc_hd__nand4_1 +A_309_ [tval_0_ _42_ _206_ _71_ _60_] _72_ d_lut_sky130_fd_sc_hd__o2111ai_1 +A_310_ [_198_ _206_ _72_] _3__0_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_311_ [tval_1_] _73_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_312_ [_65_] _74_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_313_ [_57_ _74_] _75_ d_lut_sky130_fd_sc_hd__nor2_1 +A_314_ [_59_ _75_ _56_ _54_ _42_] _76_ d_lut_sky130_fd_sc_hd__o221ai_1 +A_315_ [_75_ _69_] _77_ d_lut_sky130_fd_sc_hd__nor2_1 +A_316_ [_63_ _55_ _77_] _78_ d_lut_sky130_fd_sc_hd__nand3_1 +A_317_ [tval_1_ _42_ _206_ _78_ _76_] _79_ d_lut_sky130_fd_sc_hd__o2111ai_1 +A_318_ [_73_ _206_ _79_] _3__1_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_319_ [tint_0_] _80_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_320_ [_206_] _81_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_321_ [_62_ _61_ _56_] _82_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_322_ [_80_ _65_] _83_ d_lut_sky130_fd_sc_hd__nor2_1 +A_323_ [tint_0_ _74_] _84_ d_lut_sky130_fd_sc_hd__nor2_1 +A_324_ [_83_ _84_ _70_] _85_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_325_ [_82_ _85_ _81_] _86_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_326_ [_63_ _55_] _87_ d_lut_sky130_fd_sc_hd__nand2_1 +A_327_ [_41_ _19_] _88_ d_lut_sky130_fd_sc_hd__nor2_1 +A_328_ [_57_ _80_] _89_ d_lut_sky130_fd_sc_hd__nand2_1 +A_329_ [_57_] _90_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_330_ [_90_ tint_0_] _91_ d_lut_sky130_fd_sc_hd__nand2_1 +A_331_ [_91_ _89_ _197_] _92_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_332_ [_88_ _80_] _93_ d_lut_sky130_fd_sc_hd__nand2_1 +A_333_ [_88_ _92_ _93_ _87_] _94_ d_lut_sky130_fd_sc_hd__o211ai_1 +A_334_ [_80_ _81_ _86_ _94_] _3__2_ d_lut_sky130_fd_sc_hd__a22oi_1 +A_335_ [tint_1_] _95_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_336_ [tint_1_ _83_] _96_ d_lut_sky130_fd_sc_hd__nor2_1 +A_337_ [_67_ _96_ _70_] _97_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_338_ [_82_ _97_ _81_] _98_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_339_ [_194_ _57_] _99_ d_lut_sky130_fd_sc_hd__nand2_1 +A_340_ [_89_ tint_1_] _100_ d_lut_sky130_fd_sc_hd__nand2_1 +A_341_ [_99_ _100_ _59_] _101_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_342_ [_88_ _95_] _102_ d_lut_sky130_fd_sc_hd__nand2_1 +A_343_ [_88_ _101_ _102_ _87_] _103_ d_lut_sky130_fd_sc_hd__o211ai_1 +A_344_ [_95_ _81_ _98_ _103_] _3__3_ d_lut_sky130_fd_sc_hd__a22oi_1 +A_345_ [tint_2_] _104_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_346_ [_194_ _57_ _104_] _105_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_347_ [tint_2_ _99_] _106_ d_lut_sky130_fd_sc_hd__nor2_1 +A_348_ [_106_ _105_ _58_] _107_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_349_ [_88_ tint_2_] _108_ d_lut_sky130_fd_sc_hd__nand2_1 +A_350_ [_107_ _88_ _56_ _54_ _108_] _109_ d_lut_sky130_fd_sc_hd__o221ai_1 +A_351_ [_67_ tint_2_] _110_ d_lut_sky130_fd_sc_hd__nand2_1 +A_352_ [_65_ _66_ _104_] _111_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_353_ [_111_ _110_ _69_] _112_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_354_ [_63_ _55_ _112_] _113_ d_lut_sky130_fd_sc_hd__nand3_1 +A_355_ [_109_ _206_ _113_] _114_ d_lut_sky130_fd_sc_hd__nand3_1 +A_356_ [_104_ _206_ _114_] _3__4_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_357_ [tint_3_] _115_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_358_ [tint_4_ _68_] _116_ d_lut_sky130_fd_sc_hd__nor2_1 +A_359_ [_115_ _110_ _116_] _117_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_360_ [_82_ _117_ _81_] _118_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_361_ [_90_ _196_] _119_ d_lut_sky130_fd_sc_hd__nor2_1 +A_362_ [_115_ _106_] _120_ d_lut_sky130_fd_sc_hd__nor2_1 +A_363_ [_119_ _120_] _121_ d_lut_sky130_fd_sc_hd__nor2_1 +A_364_ [_59_ _121_] _122_ d_lut_sky130_fd_sc_hd__nor2_1 +A_365_ [_88_ _115_] _123_ d_lut_sky130_fd_sc_hd__nand2_1 +A_366_ [_88_ _122_ _123_ _87_] _124_ d_lut_sky130_fd_sc_hd__o211ai_1 +A_367_ [_115_ _81_ _118_ _124_] _3__5_ d_lut_sky130_fd_sc_hd__a22oi_1 +A_368_ [_56_ _54_ _206_ _119_ _42_] _125_ d_lut_sky130_fd_sc_hd__o2111a_1 +A_369_ [_68_ _64__bF$buf2] _126_ d_lut_sky130_fd_sc_hd__nand2_1 +A_370_ [_206_ _126_] _127_ d_lut_sky130_fd_sc_hd__nand2_1 +A_371_ [_87_ _127_ _64__bF$buf1 _125_] _3__6_ d_lut_sky130_fd_sc_hd__o22ai_1 +A_372_ [prep_0_ _203_] _2__0_ d_lut_sky130_fd_sc_hd__or2_2 +A_373_ [prep_1_] _128_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_374_ [_128_ _203_ _204_] _2__1_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_375_ [_202_ prep_2_] _129_ d_lut_sky130_fd_sc_hd__nand2_1 +A_376_ [_128_ _202_ _129_] _2__2_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_377_ [count0_0_] _130_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_378_ [_202_ count1_0_] _131_ d_lut_sky130_fd_sc_hd__nand2_1 +A_379_ [_130_ _202_ _131_] _1__0_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_380_ [count0_1_] _132_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_381_ [_202_ count1_1_] _133_ d_lut_sky130_fd_sc_hd__nand2_1 +A_382_ [_132_ _202_ _133_] _1__1_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_383_ [count0_2_] _134_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_384_ [_202_ count1_2_] _135_ d_lut_sky130_fd_sc_hd__nand2_1 +A_385_ [_134_ _202_ _135_] _1__2_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_386_ [_203_ count0_3_] _136_ d_lut_sky130_fd_sc_hd__nand2_1 +A_387_ [_202_ count1_3_] _137_ d_lut_sky130_fd_sc_hd__nand2_1 +A_388_ [_136_ _137_] _1__3_ d_lut_sky130_fd_sc_hd__nand2_1 +A_389_ [_202_ count1_4_] _138_ d_lut_sky130_fd_sc_hd__nand2_1 +A_390_ [_208_ _202_ _138_] _1__4_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_391_ [_132_ _130_] _139_ d_lut_sky130_fd_sc_hd__nor2_1 +A_392_ [_139_] _140_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_393_ [_134_ _140_] _141_ d_lut_sky130_fd_sc_hd__nor2_1 +A_394_ [_141_ count0_3_] _142_ d_lut_sky130_fd_sc_hd__nand2_1 +A_395_ [_142_] _143_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_396_ [_143_ count0_4_] _144_ d_lut_sky130_fd_sc_hd__nand2_1 +A_397_ [_144_ count0_0_ _202_] _0__0_ d_lut_sky130_fd_sc_hd__nand3_1 +A_398_ [_132_ _130_] _145_ d_lut_sky130_fd_sc_hd__nand2_1 +A_399_ [_140_ _145_] _146_ d_lut_sky130_fd_sc_hd__nand2_1 +A_400_ [_144_ _146_ _203_] _0__1_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_401_ [_134_ _139_] _147_ d_lut_sky130_fd_sc_hd__xor2_1 +A_402_ [_144_ _147_ _203_] _0__2_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_403_ [count0_3_ _141_ _202_] _148_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_404_ [_143_ _208_ _148_] _0__3_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_405_ [_142_ _208_ _203_] _0__4_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_406_ [tint_3_ tint_2_] _149_ d_lut_sky130_fd_sc_hd__nand2_1 +A_407_ [_149_ _64__bF$buf0] _217__1_ d_lut_sky130_fd_sc_hd__nand2_1 +A_408_ [tint_3_ _104_] _150_ d_lut_sky130_fd_sc_hd__nor2_1 +A_409_ [_150_] _151_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_410_ [_66_ _151_] _152_ d_lut_sky130_fd_sc_hd__nor2_1 +A_411_ [_195_ tint_1_ _80_ _64__bF$buf3] _153_ d_lut_sky130_fd_sc_hd__nand4_1 +A_412_ [_195_] _154_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_413_ [tint_4_ _154_] _155_ d_lut_sky130_fd_sc_hd__nor2_1 +A_414_ [_155_ _95_] _217__6_ d_lut_sky130_fd_sc_hd__nand2_1 +A_415_ [_217__6_ _153_] _156_ d_lut_sky130_fd_sc_hd__nand2_1 +A_416_ [_80_ _64__bF$buf2 tint_1_] _157_ d_lut_sky130_fd_sc_hd__nand3_1 +A_417_ [_157_ _151_] _158_ d_lut_sky130_fd_sc_hd__nor2_1 +A_418_ [_158_] _159_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_419_ [_66_ _154_] _160_ d_lut_sky130_fd_sc_hd__nor2_1 +A_420_ [_95_ _150_ _160_] _161_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_421_ [tint_4_ _161_ _159_] _162_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_422_ [_156_ _162_] _217__5_ d_lut_sky130_fd_sc_hd__nor2_1 +A_423_ [_217__5_] _163_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_424_ [_64__bF$buf1 _152_ _163_] _217__2_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_425_ [_155_] _217__3_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_426_ [_95_ tint_0_] _164_ d_lut_sky130_fd_sc_hd__nand2_1 +A_427_ [_104_ tint_3_] _165_ d_lut_sky130_fd_sc_hd__nand2_1 +A_428_ [_164_ _165_] _166_ d_lut_sky130_fd_sc_hd__nor2_1 +A_429_ [_166_ _64__bF$buf0] _167_ d_lut_sky130_fd_sc_hd__nand2_1 +A_430_ [_152_ _64__bF$buf3] _168_ d_lut_sky130_fd_sc_hd__nand2_1 +A_431_ [_194_] _169_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_432_ [_165_ _169_] _170_ d_lut_sky130_fd_sc_hd__nor2_1 +A_433_ [_170_ _64__bF$buf2] _171_ d_lut_sky130_fd_sc_hd__nand2_1 +A_434_ [_168_ _171_] _172_ d_lut_sky130_fd_sc_hd__nand2_1 +A_435_ [_172_ _163_] _217__9_ d_lut_sky130_fd_sc_hd__nor2_1 +A_436_ [_217__9_ _167_] _173_ d_lut_sky130_fd_sc_hd__nand2_1 +A_437_ [_173_] _217__4_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_438_ [tint_4_ _149_ _169_] _174_ d_lut_sky130_fd_sc_hd__nor3_1 +A_439_ [tint_4_ _66_ _165_] _175_ d_lut_sky130_fd_sc_hd__nor3_1 +A_440_ [_165_ _157_] _176_ d_lut_sky130_fd_sc_hd__nor2_1 +A_441_ [_174_ _175_ _176_ _173_] _217__7_ d_lut_sky130_fd_sc_hd__nor4_1 +A_442_ [_104_ _194_ _115_ _64__bF$buf1] _217__8_ d_lut_sky130_fd_sc_hd__o211ai_1 +A_443_ [_156_] _217__10_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_444_ [_176_ _173_] _217__11_ d_lut_sky130_fd_sc_hd__nor2_1 +A_445_ [tint_4_ _161_] _177_ d_lut_sky130_fd_sc_hd__nor2_1 +A_446_ [_156_ _177_] _217__12_ d_lut_sky130_fd_sc_hd__nor2_1 +A_447_ [_217__9_] _178_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_448_ [_175_ _174_] _179_ d_lut_sky130_fd_sc_hd__nor2_1 +A_449_ [_179_ _167_] _180_ d_lut_sky130_fd_sc_hd__nand2_1 +A_450_ [tint_4_ _149_ _164_ _157_ _165_] _181_ d_lut_sky130_fd_sc_hd__o32ai_1 +A_451_ [_180_ _181_ _178_] _217__13_ d_lut_sky130_fd_sc_hd__nor3_1 +A_452_ [_95_ _80_ _104_ _115_ _64__bF$buf0] _217__14_ d_lut_sky130_fd_sc_hd__a311oi_1 +A_453_ [_154_ _66_ _169_ _151_] _182_ d_lut_sky130_fd_sc_hd__o22ai_1 +A_454_ [tint_4_ _95_ _149_] _183_ d_lut_sky130_fd_sc_hd__nor3_1 +A_455_ [tint_4_ _195_ _66_ _183_] _184_ d_lut_sky130_fd_sc_hd__a31oi_1 +A_456_ [_184_] _185_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_457_ [_181_ _185_] _186_ d_lut_sky130_fd_sc_hd__nor2_1 +A_458_ [_217__9_ _167_ _179_ _186_] _187_ d_lut_sky130_fd_sc_hd__nand4_1 +A_459_ [tint_4_ _182_ _187_] _217__15_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_460_ [_194_ _195_ _64__bF$buf3] _217__16_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_461_ [_64__bF$buf2 _161_] _188_ d_lut_sky130_fd_sc_hd__nor2_1 +A_462_ [_95_ tint_0_ _64__bF$buf1 _151_] _189_ d_lut_sky130_fd_sc_hd__nor4_1 +A_463_ [_188_ _189_ _187_] _217__17_ d_lut_sky130_fd_sc_hd__nor3_1 +A_464_ [_64__bF$buf0 _195_] _217__18_ d_lut_sky130_fd_sc_hd__nor2_1 +A_465_ [_149_ _66_ _64__bF$buf3] _217__19_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_466_ [_150_ _160_ tint_4_] _190_ d_lut_sky130_fd_sc_hd__o21ai_0 +A_467_ [_186_ _179_ _190_] _191_ d_lut_sky130_fd_sc_hd__nand3_1 +A_468_ [_170_ tint_4_ _166_] _192_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_469_ [_192_ _153_ _217__6_] _193_ d_lut_sky130_fd_sc_hd__nand3_1 +A_470_ [_172_ _193_ _162_ _191_] _217__20_ d_lut_sky130_fd_sc_hd__nor4_1 +A_471_ [_195_ _95_ _64__bF$buf2] _217__21_ d_lut_sky130_fd_sc_hd__a21oi_1 +A_472_ [_188_ _187_] _217__22_ d_lut_sky130_fd_sc_hd__nor2_1 +A_473_ [_191_ _173_] _217__24_ d_lut_sky130_fd_sc_hd__nor2_1 +A_474_ [_187_] _217__25_ d_lut_sky130_fd_sc_hd__clkinv_1 +A_475_ [reset] _4_ d_lut_sky130_fd_sc_hd__clkinv_2 +A_476_ [tint_4_] trim_23_ d_lut_sky130_fd_sc_hd__buf_2 +A_477_ [_217__0_] trim_0_ d_lut_sky130_fd_sc_hd__buf_2 +A_478_ [_217__1_] trim_1_ d_lut_sky130_fd_sc_hd__buf_2 +A_479_ [_217__2_] trim_2_ d_lut_sky130_fd_sc_hd__buf_2 +A_480_ [_217__3_] trim_3_ d_lut_sky130_fd_sc_hd__buf_2 +A_481_ [_217__4_] trim_4_ d_lut_sky130_fd_sc_hd__buf_2 +A_482_ [_217__5_] trim_5_ d_lut_sky130_fd_sc_hd__buf_2 +A_483_ [_217__6_] trim_6_ d_lut_sky130_fd_sc_hd__buf_2 +A_484_ [_217__7_] trim_7_ d_lut_sky130_fd_sc_hd__buf_2 +A_485_ [_217__8_] trim_8_ d_lut_sky130_fd_sc_hd__buf_2 +A_486_ [_217__9_] trim_9_ d_lut_sky130_fd_sc_hd__buf_2 +A_487_ [_217__10_] trim_10_ d_lut_sky130_fd_sc_hd__buf_2 +A_488_ [_217__11_] trim_11_ d_lut_sky130_fd_sc_hd__buf_2 +A_489_ [_217__12_] trim_12_ d_lut_sky130_fd_sc_hd__buf_2 +A_490_ [_217__13_] trim_13_ d_lut_sky130_fd_sc_hd__buf_2 +A_491_ [_217__14_] trim_14_ d_lut_sky130_fd_sc_hd__buf_2 +A_492_ [_217__15_] trim_15_ d_lut_sky130_fd_sc_hd__buf_2 +A_493_ [_217__16_] trim_16_ d_lut_sky130_fd_sc_hd__buf_2 +A_494_ [_217__17_] trim_17_ d_lut_sky130_fd_sc_hd__buf_2 +A_495_ [_217__18_] trim_18_ d_lut_sky130_fd_sc_hd__buf_2 +A_496_ [_217__19_] trim_19_ d_lut_sky130_fd_sc_hd__buf_2 +A_497_ [_217__20_] trim_20_ d_lut_sky130_fd_sc_hd__buf_2 +A_498_ [_217__21_] trim_21_ d_lut_sky130_fd_sc_hd__buf_2 +A_499_ [_217__22_] trim_22_ d_lut_sky130_fd_sc_hd__buf_2 +A_500_ [_217__24_] trim_24_ d_lut_sky130_fd_sc_hd__buf_2 +A_501_ [_217__25_] trim_25_ d_lut_sky130_fd_sc_hd__buf_2 +A_502_ _0__0_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop +A_503_ _0__1_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop +A_504_ _0__2_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop +A_505_ _0__3_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop +A_506_ _0__4_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop +A_507_ _1__0_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop +A_508_ _1__1_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop +A_509_ _1__2_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop +A_510_ _1__3_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop +A_511_ _1__4_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop +A_512_ osc clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop +A_513_ oscbuf_0_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop +A_514_ oscbuf_1_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop +A_515_ _2__0_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop +A_516_ _2__1_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop +A_517_ _2__2_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop +A_518_ _3__0_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop +A_519_ _3__1_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop +A_520_ _3__2_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop +A_521_ _3__3_ clock_bF$buf0 NULL ~_4__bF$buf0 NULL NULL ddflop +A_522_ _3__4_ clock_bF$buf3 NULL ~_4__bF$buf3 NULL NULL ddflop +A_523_ _3__5_ clock_bF$buf2 NULL ~_4__bF$buf2 NULL NULL ddflop +A_524_ _3__6_ clock_bF$buf1 NULL ~_4__bF$buf1 NULL NULL ddflop + +.model todig_1v95 adc_bridge(in_high=1.3 in_low=0.65 rise_delay=500p fall_delay=500p) +.model toana_1v95 dac_bridge(out_high=1.95 out_low=0) + +.model ddflop d_dff(ic=0 rise_delay=50p fall_delay=50p) +.model dzero d_pulldown(load=250f) +.model done d_pullup(load=250f) + +AA2D1 [a_VPB] [VPB] todig_1v95 +AA2D2 [a_VGND] [VGND] todig_1v95 +AA2D3 [a_clock] [clock] todig_1v95 +AA2D4 [a_div_0_] [div_0_] todig_1v95 +AA2D5 [a_div_1_] [div_1_] todig_1v95 +AA2D6 [a_div_2_] [div_2_] todig_1v95 +AA2D7 [a_div_3_] [div_3_] todig_1v95 +AA2D8 [a_div_4_] [div_4_] todig_1v95 +AA2D9 [a_osc] [osc] todig_1v95 +AA2D10 [a_reset] [reset] todig_1v95 +AD2A1 [trim_0_] [a_trim_0_] toana_1v95 +AD2A2 [trim_1_] [a_trim_1_] toana_1v95 +AD2A3 [trim_2_] [a_trim_2_] toana_1v95 +AD2A4 [trim_3_] [a_trim_3_] toana_1v95 +AD2A5 [trim_4_] [a_trim_4_] toana_1v95 +AD2A6 [trim_5_] [a_trim_5_] toana_1v95 +AD2A7 [trim_6_] [a_trim_6_] toana_1v95 +AD2A8 [trim_7_] [a_trim_7_] toana_1v95 +AD2A9 [trim_8_] [a_trim_8_] toana_1v95 +AD2A10 [trim_9_] [a_trim_9_] toana_1v95 +AD2A11 [trim_10_] [a_trim_10_] toana_1v95 +AD2A12 [trim_11_] [a_trim_11_] toana_1v95 +AD2A13 [trim_12_] [a_trim_12_] toana_1v95 +AD2A14 [trim_13_] [a_trim_13_] toana_1v95 +AD2A15 [trim_14_] [a_trim_14_] toana_1v95 +AD2A16 [trim_15_] [a_trim_15_] toana_1v95 +AD2A17 [trim_16_] [a_trim_16_] toana_1v95 +AD2A18 [trim_17_] [a_trim_17_] toana_1v95 +AD2A19 [trim_18_] [a_trim_18_] toana_1v95 +AD2A20 [trim_19_] [a_trim_19_] toana_1v95 +AD2A21 [trim_20_] [a_trim_20_] toana_1v95 +AD2A22 [trim_21_] [a_trim_21_] toana_1v95 +AD2A23 [trim_22_] [a_trim_22_] toana_1v95 +AD2A24 [trim_23_] [a_trim_23_] toana_1v95 +AD2A25 [trim_24_] [a_trim_24_] toana_1v95 +AD2A26 [trim_25_] [a_trim_25_] toana_1v95 + +.ends + +* sky130_fd_sc_hd__nand2_2 (!A) | (!B) +.model d_lut_sky130_fd_sc_hd__nand2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1110") +* sky130_fd_sc_hd__inv_2 (!A) +.model d_lut_sky130_fd_sc_hd__inv_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "10") +* sky130_fd_sc_hd__nor2_2 (!A&!B) +.model d_lut_sky130_fd_sc_hd__nor2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1000") +* sky130_fd_sc_hd__conb_1 1 +* sky130_fd_sc_hd__buf_1 (A) +.model d_lut_sky130_fd_sc_hd__buf_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "01") +* sky130_fd_sc_hd__clkbuf_1 (A) +.model d_lut_sky130_fd_sc_hd__clkbuf_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "01") +* sky130_fd_sc_hd__nor2_1 (!A&!B) +.model d_lut_sky130_fd_sc_hd__nor2_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1000") +* sky130_fd_sc_hd__nand2_1 (!A) | (!B) +.model d_lut_sky130_fd_sc_hd__nand2_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1110") +* sky130_fd_sc_hd__clkinv_1 (!A) +.model d_lut_sky130_fd_sc_hd__clkinv_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "10") +* sky130_fd_sc_hd__or2_2 (A) | (B) +.model d_lut_sky130_fd_sc_hd__or2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "0111") +* sky130_fd_sc_hd__and2_2 (A&B) +.model d_lut_sky130_fd_sc_hd__and2_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "0001") +* sky130_fd_sc_hd__a21oi_1 (!A1&!B1) | (!A2&!B1) +.model d_lut_sky130_fd_sc_hd__a21oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11100000") +* sky130_fd_sc_hd__o21ai_0 (!A1&!A2) | (!B1) +.model d_lut_sky130_fd_sc_hd__o21ai_0 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11111000") +* sky130_fd_sc_hd__nand3_1 (!A) | (!B) | (!C) +.model d_lut_sky130_fd_sc_hd__nand3_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11111110") +* sky130_fd_sc_hd__o211a_1 (A1&B1&C1) | (A2&B1&C1) +.model d_lut_sky130_fd_sc_hd__o211a_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "0000000000000111") +* sky130_fd_sc_hd__o211ai_1 (!A1&!A2) | (!B1) | (!C1) +.model d_lut_sky130_fd_sc_hd__o211ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1111111111111000") +* sky130_fd_sc_hd__o21a_1 (A1&B1) | (A2&B1) +.model d_lut_sky130_fd_sc_hd__o21a_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "00000111") +* sky130_fd_sc_hd__o21bai_1 (!A1&!A2) | (B1_N) +.model d_lut_sky130_fd_sc_hd__o21bai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "10001111") +* sky130_fd_sc_hd__xnor3_4 (!A&!B&!C) | (A&B&!C) | (A&!B&C) | (!A&B&C) +.model d_lut_sky130_fd_sc_hd__xnor3_4 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "10010110") +* sky130_fd_sc_hd__o2bb2ai_1 (!B1&!B2) | (A1_N&A2_N) +.model d_lut_sky130_fd_sc_hd__o2bb2ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1111000100010001") +* sky130_fd_sc_hd__xor2_1 (A&!B) | (!A&B) +.model d_lut_sky130_fd_sc_hd__xor2_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "0110") +* sky130_fd_sc_hd__nor3_1 (!A&!B&!C) +.model d_lut_sky130_fd_sc_hd__nor3_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "10000000") +* sky130_fd_sc_hd__nand4_1 (!A) | (!B) | (!C) | (!D) +.model d_lut_sky130_fd_sc_hd__nand4_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1111111111111110") +* sky130_fd_sc_hd__a21o_2 (A1&A2) | (B1) +.model d_lut_sky130_fd_sc_hd__a21o_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "00011111") +* sky130_fd_sc_hd__a21boi_0 (!A1&B1_N) | (!A2&B1_N) +.model d_lut_sky130_fd_sc_hd__a21boi_0 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "00001110") +* sky130_fd_sc_hd__a31oi_1 (!A1&!B1) | (!A2&!B1) | (!A3&!B1) +.model d_lut_sky130_fd_sc_hd__a31oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1111111000000000") +* sky130_fd_sc_hd__o221ai_1 (!B1&!B2) | (!A1&!A2) | (!C1) +.model d_lut_sky130_fd_sc_hd__o221ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11111111111111111111100010001000") +* sky130_fd_sc_hd__o2111ai_1 (!A1&!A2) | (!B1) | (!C1) | (!D1) +.model d_lut_sky130_fd_sc_hd__o2111ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11111111111111111111111111111000") +* sky130_fd_sc_hd__a22oi_1 (!A1&!B1) | (!A1&!B2) | (!A2&!B1) | (!A2&!B2) +.model d_lut_sky130_fd_sc_hd__a22oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1110111011100000") +* sky130_fd_sc_hd__o2111a_1 (A1&B1&C1&D1) | (A2&B1&C1&D1) +.model d_lut_sky130_fd_sc_hd__o2111a_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "00000000000000000000000000000111") +* sky130_fd_sc_hd__o22ai_1 (!B1&!B2) | (!A1&!A2) +.model d_lut_sky130_fd_sc_hd__o22ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1111100010001000") +* sky130_fd_sc_hd__nor4_1 (!A&!B&!C&!D) +.model d_lut_sky130_fd_sc_hd__nor4_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "1000000000000000") +* sky130_fd_sc_hd__o32ai_1 (!A1&!A2&!A3) | (!B1&!B2) +.model d_lut_sky130_fd_sc_hd__o32ai_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11111111100000001000000010000000") +* sky130_fd_sc_hd__a311oi_1 (!A1&!B1&!C1) | (!A2&!B1&!C1) | (!A3&!B1&!C1) +.model d_lut_sky130_fd_sc_hd__a311oi_1 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "11111110000000000000000000000000") +* sky130_fd_sc_hd__clkinv_2 (!A) +.model d_lut_sky130_fd_sc_hd__clkinv_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "10") +* sky130_fd_sc_hd__buf_2 (A) +.model d_lut_sky130_fd_sc_hd__buf_2 d_lut (rise_delay=50p fall_delay=50p input_load=250f ++ table_values "01") +* sky130_fd_sc_hd__dfrtp_2 IQ +* sky130_fd_sc_hd__dfrtp_1 IQ +* sky130_fd_sc_hd__dfrtp_4 IQ +* sky130_fd_sc_hd__diode_2 (no function) +.end
diff --git a/ngspice/digital_pll/digital_pll_tb.spice b/ngspice/digital_pll/digital_pll_tb.spice new file mode 100644 index 0000000..4487369 --- /dev/null +++ b/ngspice/digital_pll/digital_pll_tb.spice
@@ -0,0 +1,49 @@ +*-------------------------------- +* Complete Digital PLL testbench +*-------------------------------- + +.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt + +.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice" + +.include "digital_pll.spice" + +.option TEMP=27 +* .option RELTOL=1.0E-2 + +* Instantiate the digital PLL + +X0 vdd vss reset osc clkp1 clkp0 div4 div3 div2 div1 div0 digital_pll + +* Power supply (note that all logic is 1.8V here) + +V0 vdd vss PWL(0.0 0.0 25n 1.8) +V1 vss 0 0.0 + +* Fixed divider value (connect resistors to power or ground) +* divider value = 16 (10MHz * 16 = 160MHz clock) + +R0 div4 vdd 1 +R1 div3 gnd 1 +R2 div2 gnd 1 +R3 div1 gnd 1 +R4 div0 gnd 1 + +* Run oscillator at 10MHz +* Because DFFs don't handle reclocking well, keep the edges sharp. + +V2 osc vss PULSE(0.0 1.8 5n 10p 10p 50n 100n) + +* Reset pulse +V3 reset vss PWL(0.0 1.8 0.1u 1.8 0.101u 0.0) + +* Transient analysis. Note that trim updates every four cycles, or about +* three updates per microsecond. To update all 17 trim bits requires +* 6us. + +.control +tran 1n 8u +plot V(osc) +plot V(clkp0) V(clkp1) +.endc +.end
diff --git a/ngspice/digital_pll/inverter_tb.spi b/ngspice/digital_pll/inverter_tb.spi new file mode 100644 index 0000000..bc57985 --- /dev/null +++ b/ngspice/digital_pll/inverter_tb.spi
@@ -0,0 +1,21 @@ +* Simple testbench mainly to check SPICE model conversion from CDL +* Plots the transient response of the smallest inverter in the HD standard cell library + +.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt +.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice" + +* .option TEMP=27 + +X0 in vss vss vdd vdd out sky130_fd_sc_hd__inv_1 + +V0 vdd vss PWL(0n 0.0 30n 1.8) +V1 vss 0 0.0 + +Vin in vss PWL(0n 0.0 100n 0.0 500n 1.8) + +* Transient analysis +.control +tran 1n 1u +plot V(in) V(out) +.endc +.end
diff --git a/ngspice/digital_pll/ring_osc2x13.spice b/ngspice/digital_pll/ring_osc2x13.spice new file mode 100644 index 0000000..d55af0e --- /dev/null +++ b/ngspice/digital_pll/ring_osc2x13.spice
@@ -0,0 +1,248 @@ +*SPICE netlist created from verilog structural netlist module ring_osc2x13 by vlog2Spice (qflow) +* Warning: This file contains <> array delimiters in net names_ +* Note: Library sky130_fd_sc_hd_spice has been removed; reference library as an +* include file from the testbench instead_ + +.subckt ring_osc2x13 VPB VGND clockp<0> clockp<1> reset trim<0> trim<1> ++ trim<2> trim<3> trim<4> trim<5> trim<6> trim<7> trim<8> trim<9> ++ trim<10> trim<11> trim<12> trim<13> trim<14> trim<15> trim<16> trim<17> ++ trim<18> trim<19> trim<20> trim<21> trim<22> trim<23> trim<24> trim<25> ++ + +X_1_ _0_<0> VGND VGND VPB VPB clockp<0> sky130_fd_sc_hd__buf_2 +X_2_ _0_<1> VGND VGND VPB VPB clockp<1> sky130_fd_sc_hd__buf_2 +Xdstage<0>_id_delaybuf0 dstage<0>_id_in VGND VGND VPB VPB dstage<0>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<0>_id_delaybuf1 dstage<0>_id_ts VGND VGND VPB VPB dstage<0>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<0>_id_delayen0 dstage<0>_id_d2 trim<0> VGND VGND VPB VPB ++ dstage<0>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<0>_id_delayen1 dstage<0>_id_d0 trim<13> VGND VGND VPB VPB ++ dstage<0>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<0>_id_delayenb0 dstage<0>_id_ts trim<0> VGND VGND VPB VPB ++ dstage<0>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<0>_id_delayenb1 dstage<0>_id_ts trim<13> VGND VGND VPB VPB ++ dstage<0>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<0>_id_delayint0 dstage<0>_id_d1 VGND VGND VPB VPB dstage<0>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<10>_id_delaybuf0 dstage<10>_id_in VGND VGND VPB VPB dstage<10>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<10>_id_delaybuf1 dstage<10>_id_ts VGND VGND VPB VPB dstage<10>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<10>_id_delayen0 dstage<10>_id_d2 trim<10> VGND VGND VPB VPB ++ dstage<10>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<10>_id_delayen1 dstage<10>_id_d0 trim<23> VGND VGND VPB VPB ++ dstage<10>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<10>_id_delayenb0 dstage<10>_id_ts trim<10> VGND VGND VPB VPB ++ dstage<10>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<10>_id_delayenb1 dstage<10>_id_ts trim<23> VGND VGND VPB VPB ++ dstage<10>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<10>_id_delayint0 dstage<10>_id_d1 VGND VGND VPB VPB dstage<10>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<11>_id_delaybuf0 dstage<10>_id_out VGND VGND VPB VPB dstage<11>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<11>_id_delaybuf1 dstage<11>_id_ts VGND VGND VPB VPB dstage<11>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<11>_id_delayen0 dstage<11>_id_d2 trim<11> VGND VGND VPB VPB ++ dstage<11>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<11>_id_delayen1 dstage<11>_id_d0 trim<24> VGND VGND VPB VPB ++ dstage<11>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<11>_id_delayenb0 dstage<11>_id_ts trim<11> VGND VGND VPB VPB ++ dstage<11>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<11>_id_delayenb1 dstage<11>_id_ts trim<24> VGND VGND VPB VPB ++ dstage<11>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<11>_id_delayint0 dstage<11>_id_d1 VGND VGND VPB VPB dstage<11>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<1>_id_delaybuf0 dstage<0>_id_out VGND VGND VPB VPB dstage<1>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<1>_id_delaybuf1 dstage<1>_id_ts VGND VGND VPB VPB dstage<1>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<1>_id_delayen0 dstage<1>_id_d2 trim<1> VGND VGND VPB VPB ++ dstage<1>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<1>_id_delayen1 dstage<1>_id_d0 trim<14> VGND VGND VPB VPB ++ dstage<1>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<1>_id_delayenb0 dstage<1>_id_ts trim<1> VGND VGND VPB VPB ++ dstage<1>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<1>_id_delayenb1 dstage<1>_id_ts trim<14> VGND VGND VPB VPB ++ dstage<1>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<1>_id_delayint0 dstage<1>_id_d1 VGND VGND VPB VPB dstage<1>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<2>_id_delaybuf0 dstage<1>_id_out VGND VGND VPB VPB dstage<2>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<2>_id_delaybuf1 dstage<2>_id_ts VGND VGND VPB VPB dstage<2>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<2>_id_delayen0 dstage<2>_id_d2 trim<2> VGND VGND VPB VPB ++ dstage<2>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<2>_id_delayen1 dstage<2>_id_d0 trim<15> VGND VGND VPB VPB ++ dstage<2>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<2>_id_delayenb0 dstage<2>_id_ts trim<2> VGND VGND VPB VPB ++ dstage<2>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<2>_id_delayenb1 dstage<2>_id_ts trim<15> VGND VGND VPB VPB ++ dstage<2>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<2>_id_delayint0 dstage<2>_id_d1 VGND VGND VPB VPB dstage<2>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<3>_id_delaybuf0 dstage<2>_id_out VGND VGND VPB VPB dstage<3>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<3>_id_delaybuf1 dstage<3>_id_ts VGND VGND VPB VPB dstage<3>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<3>_id_delayen0 dstage<3>_id_d2 trim<3> VGND VGND VPB VPB ++ dstage<3>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<3>_id_delayen1 dstage<3>_id_d0 trim<16> VGND VGND VPB VPB ++ dstage<3>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<3>_id_delayenb0 dstage<3>_id_ts trim<3> VGND VGND VPB VPB ++ dstage<3>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<3>_id_delayenb1 dstage<3>_id_ts trim<16> VGND VGND VPB VPB ++ dstage<3>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<3>_id_delayint0 dstage<3>_id_d1 VGND VGND VPB VPB dstage<3>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<4>_id_delaybuf0 dstage<3>_id_out VGND VGND VPB VPB dstage<4>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<4>_id_delaybuf1 dstage<4>_id_ts VGND VGND VPB VPB dstage<4>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<4>_id_delayen0 dstage<4>_id_d2 trim<4> VGND VGND VPB VPB ++ dstage<4>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<4>_id_delayen1 dstage<4>_id_d0 trim<17> VGND VGND VPB VPB ++ dstage<4>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<4>_id_delayenb0 dstage<4>_id_ts trim<4> VGND VGND VPB VPB ++ dstage<4>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<4>_id_delayenb1 dstage<4>_id_ts trim<17> VGND VGND VPB VPB ++ dstage<4>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<4>_id_delayint0 dstage<4>_id_d1 VGND VGND VPB VPB dstage<4>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<5>_id_delaybuf0 dstage<4>_id_out VGND VGND VPB VPB dstage<5>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<5>_id_delaybuf1 dstage<5>_id_ts VGND VGND VPB VPB dstage<5>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<5>_id_delayen0 dstage<5>_id_d2 trim<5> VGND VGND VPB VPB ++ dstage<5>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<5>_id_delayen1 dstage<5>_id_d0 trim<18> VGND VGND VPB VPB ++ dstage<5>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<5>_id_delayenb0 dstage<5>_id_ts trim<5> VGND VGND VPB VPB ++ dstage<5>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<5>_id_delayenb1 dstage<5>_id_ts trim<18> VGND VGND VPB VPB ++ dstage<5>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<5>_id_delayint0 dstage<5>_id_d1 VGND VGND VPB VPB dstage<5>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<6>_id_delaybuf0 dstage<5>_id_out VGND VGND VPB VPB dstage<6>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<6>_id_delaybuf1 dstage<6>_id_ts VGND VGND VPB VPB dstage<6>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<6>_id_delayen0 dstage<6>_id_d2 trim<6> VGND VGND VPB VPB ++ dstage<6>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<6>_id_delayen1 dstage<6>_id_d0 trim<19> VGND VGND VPB VPB ++ dstage<6>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<6>_id_delayenb0 dstage<6>_id_ts trim<6> VGND VGND VPB VPB ++ dstage<6>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<6>_id_delayenb1 dstage<6>_id_ts trim<19> VGND VGND VPB VPB ++ dstage<6>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<6>_id_delayint0 dstage<6>_id_d1 VGND VGND VPB VPB dstage<6>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<7>_id_delaybuf0 dstage<6>_id_out VGND VGND VPB VPB dstage<7>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<7>_id_delaybuf1 dstage<7>_id_ts VGND VGND VPB VPB dstage<7>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<7>_id_delayen0 dstage<7>_id_d2 trim<7> VGND VGND VPB VPB ++ dstage<7>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<7>_id_delayen1 dstage<7>_id_d0 trim<20> VGND VGND VPB VPB ++ dstage<7>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<7>_id_delayenb0 dstage<7>_id_ts trim<7> VGND VGND VPB VPB ++ dstage<7>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<7>_id_delayenb1 dstage<7>_id_ts trim<20> VGND VGND VPB VPB ++ dstage<7>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<7>_id_delayint0 dstage<7>_id_d1 VGND VGND VPB VPB dstage<7>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<8>_id_delaybuf0 dstage<7>_id_out VGND VGND VPB VPB dstage<8>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<8>_id_delaybuf1 dstage<8>_id_ts VGND VGND VPB VPB dstage<8>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<8>_id_delayen0 dstage<8>_id_d2 trim<8> VGND VGND VPB VPB ++ dstage<8>_id_out ++ sky130_fd_sc_hd__einvp_2 +Xdstage<8>_id_delayen1 dstage<8>_id_d0 trim<21> VGND VGND VPB VPB ++ dstage<8>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<8>_id_delayenb0 dstage<8>_id_ts trim<8> VGND VGND VPB VPB ++ dstage<8>_id_out ++ sky130_fd_sc_hd__einvn_8 +Xdstage<8>_id_delayenb1 dstage<8>_id_ts trim<21> VGND VGND VPB VPB ++ dstage<8>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<8>_id_delayint0 dstage<8>_id_d1 VGND VGND VPB VPB dstage<8>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xdstage<9>_id_delaybuf0 dstage<8>_id_out VGND VGND VPB VPB dstage<9>_id_ts sky130_fd_sc_hd__clkbuf_2 +Xdstage<9>_id_delaybuf1 dstage<9>_id_ts VGND VGND VPB VPB dstage<9>_id_d0 sky130_fd_sc_hd__clkbuf_1 +Xdstage<9>_id_delayen0 dstage<9>_id_d2 trim<9> VGND VGND VPB VPB ++ dstage<10>_id_in ++ sky130_fd_sc_hd__einvp_2 +Xdstage<9>_id_delayen1 dstage<9>_id_d0 trim<22> VGND VGND VPB VPB ++ dstage<9>_id_d1 ++ sky130_fd_sc_hd__einvp_2 +Xdstage<9>_id_delayenb0 dstage<9>_id_ts trim<9> VGND VGND VPB VPB ++ dstage<10>_id_in ++ sky130_fd_sc_hd__einvn_8 +Xdstage<9>_id_delayenb1 dstage<9>_id_ts trim<22> VGND VGND VPB VPB ++ dstage<9>_id_d1 ++ sky130_fd_sc_hd__einvn_4 +Xdstage<9>_id_delayint0 dstage<9>_id_d1 VGND VGND VPB VPB dstage<9>_id_d2 sky130_fd_sc_hd__clkinv_1 +Xibufp00 dstage<0>_id_in VGND VGND VPB VPB c<0> sky130_fd_sc_hd__clkinv_2 +Xibufp01 c<0> VGND VGND VPB VPB _0_<0> sky130_fd_sc_hd__clkinv_8 +Xibufp10 dstage<5>_id_out VGND VGND VPB VPB c<1> sky130_fd_sc_hd__clkinv_2 +Xibufp11 c<1> VGND VGND VPB VPB _0_<1> sky130_fd_sc_hd__clkinv_8 +Xiss_const1 VGND VGND VPB VPB iss_one _noconnect_1_ sky130_fd_sc_hd__conb_1 +Xiss_ctrlen0 reset trim<12> VGND VGND VPB VPB ++ iss_ctrl0 ++ sky130_fd_sc_hd__or2_2 +Xiss_delaybuf0 dstage<11>_id_out VGND VGND VPB VPB iss_d0 sky130_fd_sc_hd__clkbuf_1 +Xiss_delayen0 iss_d2 trim<12> VGND VGND VPB VPB ++ dstage<0>_id_in ++ sky130_fd_sc_hd__einvp_2 +Xiss_delayen1 iss_d0 trim<25> VGND VGND VPB VPB ++ iss_d1 ++ sky130_fd_sc_hd__einvp_2 +Xiss_delayenb0 dstage<11>_id_out iss_ctrl0 VGND VGND VPB VPB ++ dstage<0>_id_in ++ sky130_fd_sc_hd__einvn_8 +Xiss_delayenb1 dstage<11>_id_out trim<25> VGND VGND VPB VPB ++ iss_d1 ++ sky130_fd_sc_hd__einvn_4 +Xiss_delayint0 iss_d1 VGND VGND VPB VPB iss_d2 sky130_fd_sc_hd__clkinv_1 +Xiss_reseten0 iss_one reset VGND VGND VPB VPB ++ dstage<0>_id_in ++ sky130_fd_sc_hd__einvp_1 +Xantenna_0 reset VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<25> trim<25> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<24> trim<24> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<23> trim<23> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<22> trim<22> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<21> trim<21> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<20> trim<20> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<19> trim<19> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<18> trim<18> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<17> trim<17> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<16> trim<16> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<15> trim<15> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<14> trim<14> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<13> trim<13> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<12> trim<12> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<11> trim<11> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<10> trim<10> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<9> trim<9> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<8> trim<8> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<7> trim<7> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<6> trim<6> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<5> trim<5> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<4> trim<4> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<3> trim<3> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<2> trim<2> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<1> trim<1> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1<0> trim<0> VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 + +.ends +.end
diff --git a/ngspice/digital_pll/ring_osc2x13.spice.bak b/ngspice/digital_pll/ring_osc2x13.spice.bak new file mode 100644 index 0000000..1d5208a --- /dev/null +++ b/ngspice/digital_pll/ring_osc2x13.spice.bak
@@ -0,0 +1,248 @@ +*SPICE netlist created from verilog structural netlist module ring_osc2x13 by vlog2Spice (qflow) +* Warning: This file contains [] array delimiters in net names. +* Note: Library sky130_fd_sc_hd.spice has been removed; reference library as an +* include file from the testbench instead. + +.subckt ring_osc2x13 VPB VGND clockp[0] clockp[1] reset trim[0] trim[1] ++ trim[2] trim[3] trim[4] trim[5] trim[6] trim[7] trim[8] trim[9] ++ trim[10] trim[11] trim[12] trim[13] trim[14] trim[15] trim[16] trim[17] ++ trim[18] trim[19] trim[20] trim[21] trim[22] trim[23] trim[24] trim[25] ++ + +X_1_ _0_[0] VGND VGND VPB VPB clockp[0] sky130_fd_sc_hd__buf_2 +X_2_ _0_[1] VGND VGND VPB VPB clockp[1] sky130_fd_sc_hd__buf_2 +X\dstage[0].id.delaybuf0 \dstage[0].id.in\ VGND VGND VPB VPB \dstage[0].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[0].id.delaybuf1 \dstage[0].id.ts\ VGND VGND VPB VPB \dstage[0].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[0].id.delayen0 \dstage[0].id.d2\ trim[0] VGND VGND VPB VPB ++ \dstage[0].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[0].id.delayen1 \dstage[0].id.d0\ trim[13] VGND VGND VPB VPB ++ \dstage[0].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[0].id.delayenb0 \dstage[0].id.ts\ trim[0] VGND VGND VPB VPB ++ \dstage[0].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[0].id.delayenb1 \dstage[0].id.ts\ trim[13] VGND VGND VPB VPB ++ \dstage[0].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[0].id.delayint0 \dstage[0].id.d1\ VGND VGND VPB VPB \dstage[0].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[10].id.delaybuf0 \dstage[10].id.in\ VGND VGND VPB VPB \dstage[10].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[10].id.delaybuf1 \dstage[10].id.ts\ VGND VGND VPB VPB \dstage[10].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[10].id.delayen0 \dstage[10].id.d2\ trim[10] VGND VGND VPB VPB ++ \dstage[10].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[10].id.delayen1 \dstage[10].id.d0\ trim[23] VGND VGND VPB VPB ++ \dstage[10].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[10].id.delayenb0 \dstage[10].id.ts\ trim[10] VGND VGND VPB VPB ++ \dstage[10].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[10].id.delayenb1 \dstage[10].id.ts\ trim[23] VGND VGND VPB VPB ++ \dstage[10].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[10].id.delayint0 \dstage[10].id.d1\ VGND VGND VPB VPB \dstage[10].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[11].id.delaybuf0 \dstage[10].id.out\ VGND VGND VPB VPB \dstage[11].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[11].id.delaybuf1 \dstage[11].id.ts\ VGND VGND VPB VPB \dstage[11].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[11].id.delayen0 \dstage[11].id.d2\ trim[11] VGND VGND VPB VPB ++ \dstage[11].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[11].id.delayen1 \dstage[11].id.d0\ trim[24] VGND VGND VPB VPB ++ \dstage[11].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[11].id.delayenb0 \dstage[11].id.ts\ trim[11] VGND VGND VPB VPB ++ \dstage[11].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[11].id.delayenb1 \dstage[11].id.ts\ trim[24] VGND VGND VPB VPB ++ \dstage[11].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[11].id.delayint0 \dstage[11].id.d1\ VGND VGND VPB VPB \dstage[11].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[1].id.delaybuf0 \dstage[0].id.out\ VGND VGND VPB VPB \dstage[1].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[1].id.delaybuf1 \dstage[1].id.ts\ VGND VGND VPB VPB \dstage[1].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[1].id.delayen0 \dstage[1].id.d2\ trim[1] VGND VGND VPB VPB ++ \dstage[1].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[1].id.delayen1 \dstage[1].id.d0\ trim[14] VGND VGND VPB VPB ++ \dstage[1].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[1].id.delayenb0 \dstage[1].id.ts\ trim[1] VGND VGND VPB VPB ++ \dstage[1].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[1].id.delayenb1 \dstage[1].id.ts\ trim[14] VGND VGND VPB VPB ++ \dstage[1].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[1].id.delayint0 \dstage[1].id.d1\ VGND VGND VPB VPB \dstage[1].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[2].id.delaybuf0 \dstage[1].id.out\ VGND VGND VPB VPB \dstage[2].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[2].id.delaybuf1 \dstage[2].id.ts\ VGND VGND VPB VPB \dstage[2].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[2].id.delayen0 \dstage[2].id.d2\ trim[2] VGND VGND VPB VPB ++ \dstage[2].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[2].id.delayen1 \dstage[2].id.d0\ trim[15] VGND VGND VPB VPB ++ \dstage[2].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[2].id.delayenb0 \dstage[2].id.ts\ trim[2] VGND VGND VPB VPB ++ \dstage[2].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[2].id.delayenb1 \dstage[2].id.ts\ trim[15] VGND VGND VPB VPB ++ \dstage[2].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[2].id.delayint0 \dstage[2].id.d1\ VGND VGND VPB VPB \dstage[2].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[3].id.delaybuf0 \dstage[2].id.out\ VGND VGND VPB VPB \dstage[3].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[3].id.delaybuf1 \dstage[3].id.ts\ VGND VGND VPB VPB \dstage[3].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[3].id.delayen0 \dstage[3].id.d2\ trim[3] VGND VGND VPB VPB ++ \dstage[3].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[3].id.delayen1 \dstage[3].id.d0\ trim[16] VGND VGND VPB VPB ++ \dstage[3].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[3].id.delayenb0 \dstage[3].id.ts\ trim[3] VGND VGND VPB VPB ++ \dstage[3].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[3].id.delayenb1 \dstage[3].id.ts\ trim[16] VGND VGND VPB VPB ++ \dstage[3].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[3].id.delayint0 \dstage[3].id.d1\ VGND VGND VPB VPB \dstage[3].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[4].id.delaybuf0 \dstage[3].id.out\ VGND VGND VPB VPB \dstage[4].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[4].id.delaybuf1 \dstage[4].id.ts\ VGND VGND VPB VPB \dstage[4].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[4].id.delayen0 \dstage[4].id.d2\ trim[4] VGND VGND VPB VPB ++ \dstage[4].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[4].id.delayen1 \dstage[4].id.d0\ trim[17] VGND VGND VPB VPB ++ \dstage[4].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[4].id.delayenb0 \dstage[4].id.ts\ trim[4] VGND VGND VPB VPB ++ \dstage[4].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[4].id.delayenb1 \dstage[4].id.ts\ trim[17] VGND VGND VPB VPB ++ \dstage[4].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[4].id.delayint0 \dstage[4].id.d1\ VGND VGND VPB VPB \dstage[4].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[5].id.delaybuf0 \dstage[4].id.out\ VGND VGND VPB VPB \dstage[5].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[5].id.delaybuf1 \dstage[5].id.ts\ VGND VGND VPB VPB \dstage[5].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[5].id.delayen0 \dstage[5].id.d2\ trim[5] VGND VGND VPB VPB ++ \dstage[5].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[5].id.delayen1 \dstage[5].id.d0\ trim[18] VGND VGND VPB VPB ++ \dstage[5].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[5].id.delayenb0 \dstage[5].id.ts\ trim[5] VGND VGND VPB VPB ++ \dstage[5].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[5].id.delayenb1 \dstage[5].id.ts\ trim[18] VGND VGND VPB VPB ++ \dstage[5].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[5].id.delayint0 \dstage[5].id.d1\ VGND VGND VPB VPB \dstage[5].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[6].id.delaybuf0 \dstage[5].id.out\ VGND VGND VPB VPB \dstage[6].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[6].id.delaybuf1 \dstage[6].id.ts\ VGND VGND VPB VPB \dstage[6].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[6].id.delayen0 \dstage[6].id.d2\ trim[6] VGND VGND VPB VPB ++ \dstage[6].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[6].id.delayen1 \dstage[6].id.d0\ trim[19] VGND VGND VPB VPB ++ \dstage[6].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[6].id.delayenb0 \dstage[6].id.ts\ trim[6] VGND VGND VPB VPB ++ \dstage[6].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[6].id.delayenb1 \dstage[6].id.ts\ trim[19] VGND VGND VPB VPB ++ \dstage[6].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[6].id.delayint0 \dstage[6].id.d1\ VGND VGND VPB VPB \dstage[6].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[7].id.delaybuf0 \dstage[6].id.out\ VGND VGND VPB VPB \dstage[7].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[7].id.delaybuf1 \dstage[7].id.ts\ VGND VGND VPB VPB \dstage[7].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[7].id.delayen0 \dstage[7].id.d2\ trim[7] VGND VGND VPB VPB ++ \dstage[7].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[7].id.delayen1 \dstage[7].id.d0\ trim[20] VGND VGND VPB VPB ++ \dstage[7].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[7].id.delayenb0 \dstage[7].id.ts\ trim[7] VGND VGND VPB VPB ++ \dstage[7].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[7].id.delayenb1 \dstage[7].id.ts\ trim[20] VGND VGND VPB VPB ++ \dstage[7].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[7].id.delayint0 \dstage[7].id.d1\ VGND VGND VPB VPB \dstage[7].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[8].id.delaybuf0 \dstage[7].id.out\ VGND VGND VPB VPB \dstage[8].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[8].id.delaybuf1 \dstage[8].id.ts\ VGND VGND VPB VPB \dstage[8].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[8].id.delayen0 \dstage[8].id.d2\ trim[8] VGND VGND VPB VPB ++ \dstage[8].id.out\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[8].id.delayen1 \dstage[8].id.d0\ trim[21] VGND VGND VPB VPB ++ \dstage[8].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[8].id.delayenb0 \dstage[8].id.ts\ trim[8] VGND VGND VPB VPB ++ \dstage[8].id.out\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[8].id.delayenb1 \dstage[8].id.ts\ trim[21] VGND VGND VPB VPB ++ \dstage[8].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[8].id.delayint0 \dstage[8].id.d1\ VGND VGND VPB VPB \dstage[8].id.d2\ sky130_fd_sc_hd__clkinv_1 +X\dstage[9].id.delaybuf0 \dstage[8].id.out\ VGND VGND VPB VPB \dstage[9].id.ts\ sky130_fd_sc_hd__clkbuf_2 +X\dstage[9].id.delaybuf1 \dstage[9].id.ts\ VGND VGND VPB VPB \dstage[9].id.d0\ sky130_fd_sc_hd__clkbuf_1 +X\dstage[9].id.delayen0 \dstage[9].id.d2\ trim[9] VGND VGND VPB VPB ++ \dstage[10].id.in\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[9].id.delayen1 \dstage[9].id.d0\ trim[22] VGND VGND VPB VPB ++ \dstage[9].id.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\dstage[9].id.delayenb0 \dstage[9].id.ts\ trim[9] VGND VGND VPB VPB ++ \dstage[10].id.in\ ++ sky130_fd_sc_hd__einvn_8 +X\dstage[9].id.delayenb1 \dstage[9].id.ts\ trim[22] VGND VGND VPB VPB ++ \dstage[9].id.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\dstage[9].id.delayint0 \dstage[9].id.d1\ VGND VGND VPB VPB \dstage[9].id.d2\ sky130_fd_sc_hd__clkinv_1 +Xibufp00 \dstage[0].id.in\ VGND VGND VPB VPB c[0] sky130_fd_sc_hd__clkinv_2 +Xibufp01 c[0] VGND VGND VPB VPB _0_[0] sky130_fd_sc_hd__clkinv_8 +Xibufp10 \dstage[5].id.out\ VGND VGND VPB VPB c[1] sky130_fd_sc_hd__clkinv_2 +Xibufp11 c[1] VGND VGND VPB VPB _0_[1] sky130_fd_sc_hd__clkinv_8 +X\iss.const1 VGND VGND VPB VPB \iss.one\ _noconnect_1_ sky130_fd_sc_hd__conb_1 +X\iss.ctrlen0 reset trim[12] VGND VGND VPB VPB ++ \iss.ctrl0\ ++ sky130_fd_sc_hd__or2_2 +X\iss.delaybuf0 \dstage[11].id.out\ VGND VGND VPB VPB \iss.d0\ sky130_fd_sc_hd__clkbuf_1 +X\iss.delayen0 \iss.d2\ trim[12] VGND VGND VPB VPB ++ \dstage[0].id.in\ ++ sky130_fd_sc_hd__einvp_2 +X\iss.delayen1 \iss.d0\ trim[25] VGND VGND VPB VPB ++ \iss.d1\ ++ sky130_fd_sc_hd__einvp_2 +X\iss.delayenb0 \dstage[11].id.out\ \iss.ctrl0\ VGND VGND VPB VPB ++ \dstage[0].id.in\ ++ sky130_fd_sc_hd__einvn_8 +X\iss.delayenb1 \dstage[11].id.out\ trim[25] VGND VGND VPB VPB ++ \iss.d1\ ++ sky130_fd_sc_hd__einvn_4 +X\iss.delayint0 \iss.d1\ VGND VGND VPB VPB \iss.d2\ sky130_fd_sc_hd__clkinv_1 +X\iss.reseten0 \iss.one\ reset VGND VGND VPB VPB ++ \dstage[0].id.in\ ++ sky130_fd_sc_hd__einvp_1 +Xantenna_0 reset VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[25] trim[25] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[24] trim[24] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[23] trim[23] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[22] trim[22] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[21] trim[21] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[20] trim[20] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[19] trim[19] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[18] trim[18] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[17] trim[17] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[16] trim[16] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[15] trim[15] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[14] trim[14] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[13] trim[13] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[12] trim[12] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[11] trim[11] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[10] trim[10] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[9] trim[9] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[8] trim[8] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[7] trim[7] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[6] trim[6] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[5] trim[5] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[4] trim[4] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[3] trim[3] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[2] trim[2] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[1] trim[1] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 +Xantenna_1[0] trim[0] VGND VGND VPB VPB sky130_fd_sc_hd__diode_2 + +.ends +.end
diff --git a/ngspice/digital_pll/ring_osc2x13_tb.spice b/ngspice/digital_pll/ring_osc2x13_tb.spice new file mode 100644 index 0000000..248051b --- /dev/null +++ b/ngspice/digital_pll/ring_osc2x13_tb.spice
@@ -0,0 +1,42 @@ +* Ring oscillator testbench---simple check of ring oscillator +* at several trim levels + +.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt + +.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice" + +.include "ring_osc2x13.spice" + +.option TEMP=27 +* .option RELTOL=1.0E-1 +* .option RSHUNT=1.0E20 + +* Instantiate the ring oscillator +* Tie trims together in four sets + +X0 vdd vss clockp0 clockp1 reset trim0 trim1 trim0 trim1 trim0 trim1 trim0 ++ trim1 trim0 trim1 trim0 trim1 trim0 trim3 trim2 trim3 trim2 trim3 trim2 ++ trim3 trim2 trim3 trim2 trim3 trim2 trim3 ring_osc2x13 + +* Power supply (note that all logic is 1.8V here) + +V0 vdd vss PWL(0n 0.0 30n 1.8) +V1 vss 0 0.0 + +* Trim values (connect resistors to power or ground) +* divider value = 12 + +V2 trim0 gnd PULSE(0.0 1.8 200n 2n 2n 1u 2u) +V3 trim1 gnd PULSE(0.0 1.8 400n 2n 2n 1u 2u) +V4 trim2 gnd PULSE(0.0 1.8 600n 2n 2n 1u 2u) +V5 trim3 gnd PULSE(0.0 1.8 800n 2n 2n 1u 2u) + +* Reset +V6 reset gnd PWL(0n 1.8 48n 1.8 50n 0.0) + +* Transient analysis +.control +tran 100p 1u +plot V(clockp0) V(clockp1) +.endc +.end
diff --git a/ngspice/digital_pll/ring_osc2x13_tb2.spice b/ngspice/digital_pll/ring_osc2x13_tb2.spice new file mode 100644 index 0000000..5b32330 --- /dev/null +++ b/ngspice/digital_pll/ring_osc2x13_tb2.spice
@@ -0,0 +1,64 @@ +* Ring oscillator testbench---simple check of ring oscillator +* at several trim levels + +.lib "/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice" tt + +.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice" + +.include "ring_osc2x13.spice" + +.option TEMP=27 +* .option RELTOL=1.0E-1 +* .option RSHUNT=1.0E20 + +* Instantiate the ring oscillator +* Tie trims together in four sets + +X0 vdd vss clockp0 clockp1 reset trim00 trim01 trim02 trim03 trim04 trim05 trim06 ++ trim07 trim08 trim09 trim10 trim11 trim12 trim13 trim14 trim15 trim16 trim17 ++ trim18 trim19 trim20 trim21 trim22 trim23 trim24 trim25 ring_osc2x13 + +* Power supply (note that all logic is 1.8V here) + +V00 vdd vss PWL(0n 0.0 30n 1.8) +V01 vss 0 0.0 + +* Trim values (connect resistors to power or ground) +* divider value = 12 + +V02 trim00 gnd PULSE(0.0 1.8 40n 2n 2n 1u 2u) +V03 trim01 gnd PULSE(0.0 1.8 80n 2n 2n 1u 2u) +V04 trim02 gnd PULSE(0.0 1.8 120n 2n 2n 1u 2u) +V05 trim03 gnd PULSE(0.0 1.8 160n 2n 2n 1u 2u) +V06 trim04 gnd PULSE(0.0 1.8 200n 2n 2n 1u 2u) +V07 trim05 gnd PULSE(0.0 1.8 240n 2n 2n 1u 2u) +V08 trim06 gnd PULSE(0.0 1.8 280n 2n 2n 1u 2u) +V09 trim07 gnd PULSE(0.0 1.8 320n 2n 2n 1u 2u) +V10 trim08 gnd PULSE(0.0 1.8 360n 2n 2n 1u 2u) +V11 trim09 gnd PULSE(0.0 1.8 400n 2n 2n 1u 2u) +V12 trim10 gnd PULSE(0.0 1.8 440n 2n 2n 1u 2u) +V13 trim11 gnd PULSE(0.0 1.8 480n 2n 2n 1u 2u) +V14 trim12 gnd PULSE(0.0 1.8 520n 2n 2n 1u 2u) +V15 trim13 gnd PULSE(0.0 1.8 560n 2n 2n 1u 2u) +V16 trim14 gnd PULSE(0.0 1.8 600n 2n 2n 1u 2u) +V17 trim15 gnd PULSE(0.0 1.8 640n 2n 2n 1u 2u) +V18 trim16 gnd PULSE(0.0 1.8 680n 2n 2n 1u 2u) +V19 trim17 gnd PULSE(0.0 1.8 720n 2n 2n 1u 2u) +V20 trim18 gnd PULSE(0.0 1.8 760n 2n 2n 1u 2u) +V21 trim19 gnd PULSE(0.0 1.8 800n 2n 2n 1u 2u) +V22 trim20 gnd PULSE(0.0 1.8 840n 2n 2n 1u 2u) +V23 trim21 gnd PULSE(0.0 1.8 880n 2n 2n 1u 2u) +V24 trim22 gnd PULSE(0.0 1.8 920n 2n 2n 1u 2u) +V25 trim23 gnd PULSE(0.0 1.8 960n 2n 2n 1u 2u) +V26 trim24 gnd PULSE(0.0 1.8 800n 2n 2n 1u 2u) +V27 trim25 gnd PULSE(0.0 1.8 840n 2n 2n 1u 2u) + +* Reset +V6 reset gnd PWL(0n 1.8 8n 1.8 10n 0.0) + +* Transient analysis +.control +tran 100p 1u +plot V(clockp0) V(clockp1) +.endc +.end
diff --git a/ngspice/simple_por/current_test.spice b/ngspice/simple_por/current_test.spice new file mode 100644 index 0000000..606eb2d --- /dev/null +++ b/ngspice/simple_por/current_test.spice
@@ -0,0 +1,70 @@ +*------------------------------------------------------------------- +* Simple POR circuit for Caravel current mirror test +*------------------------------------------------------------------- + +.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt + +* Note: 20 resistors of length 25um connected in series +Xres1 vdda vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500 +Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=149 + +* voltage sources at 0V for measuring current in each branch + +Vm1 vssm1 vss DC=0 +Vm2 vdda vddm2 DC=0 +Vm3 vdda vddm3 DC=0 +Vm4 vssm4 vss DC=0 +Vm5 vssm5 vss DC=0 +Vm6 vdda vddm6 DC=0 +Vm7 vdda vddm7 DC=0 + +* D G S B +Xm1 casc1 vin vssm1 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc1 mir1 casc1 casc1 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm2 mir1 mir1 vddm2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8 +Xm3 mir2 mir1 vddm3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc2 casc2 casc1 mir2 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm4 casc2 casc2 vssm4 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm5 casc3 casc2 vssm5 vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc3 mir3 casc3 casc3 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm6 mir3 mir3 vddm6 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm7 mir4 mir3 vddm7 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc4 vcap casc3 mir4 vdda sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 + +* Check branch currents in each mirror branch. +* 1st branch should be 240nA +* 2nd branch should be 30nA +* 3rd branch should be 4.3nA +* 4th branch should be 612pA +* +* Result: vin sits at 0.7590 (close to 0.7575 target) +* I(Vm1/2) = 202.80 nA +* I(Vm3/4) = 26.10 nA (should be /8) actually /7.77 +* I(Vm5/6) = 4.58 nA (should be /7) actually /5.70 +* I(Vm7) = 0.67 pA (should be /7) actually /6.80 + +*---------------------------- +* Testbench circuit +*---------------------------- +Vpwr vdda vss DC=3.3 +Rgnd vss 0 0.01 +Rload vcap vss 1MEG +*---------------------------- + +*---------------------------- +* Testbench control +*---------------------------- +.control +op +print V(vin) +print I(Vm1) +print I(Vm2) +print I(Vm3) +print I(Vm4) +print I(Vm5) +print I(Vm6) +print I(Vm7) +.endc + +.end +
diff --git a/ngspice/simple_por/simple_por.spice b/ngspice/simple_por/simple_por.spice new file mode 100644 index 0000000..18065b8 --- /dev/null +++ b/ngspice/simple_por/simple_por.spice
@@ -0,0 +1,73 @@ +*------------------------------------------------------------------- +* Simple POR circuit for Caravel +*------------------------------------------------------------------- +* +* Architecture: +* +* Resistive divider sets mvnfet transistor gate voltage to ??V +* mvnfet current is 240nA nominal +* mvnfet drives current mirror at 1/400x to 600pA through mvpfet +* current feeds 1.84pF capacitor (double MiM at 30um x 30um) +* voltage across capacitor is input to chain of two schmitt trigger +* inverters. +* +* Q = C * V = I * dt +* +* t = C * V / I = 1.84pF * 3.3V / 600pA = 10ms +* +* ~400x step-down done by mirroring 1:8, 1:7, 1:7 (= 392) +* +* From DC sweep test result, V = 0.7575 on the transtor gate at vin +* Resistor divider at fraction 0.23. +* This yields resistor lengths of 500 on top, 149 on the bottom +* +* Actual response of this circuit by ngspice simulation is 15ms. +*------------------------------------------------------------------- + +.subckt simple_por vdd3v3 vdd1v8 vss porb_h por_l porb_l + +Xcap1 vcap vss sky130_fd_pr__cap_mim_m3_1 l=30 w=30 +Xcap2 vss vcap sky130_fd_pr__cap_mim_m3_2 l=30 w=30 + +* Note: 20 resistors of length 25um connected in series +Xres1 vdd3v3 vin vss sky130_fd_pr__res_xhigh_po_0p69 l=500 +* Note: 6 resistors of length 25um connected in series +Xres2 vin vss vss sky130_fd_pr__res_xhigh_po_0p69 l=150 +* Note: 2 dummy resistors of length 25um +Xres3 vss vss vss sky130_fd_pr__res_xhigh_po_0p69 l=50 + +* Triple current mirror, ratios 8:1, 7:1, and 7:1, with p-cascodes +* D G S B +Xm1 casc1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc1 mir1 casc1 casc1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm2 mir1 mir1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=8 +Xm3 mir2 mir1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc2 casc2 casc1 mir2 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm4 casc2 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm5 casc3 casc2 vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc3 mir3 casc3 casc3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xm6 mir3 mir3 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=7 +Xm7 mir4 mir3 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 +Xc4 vcap casc3 mir4 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 w=2 l=0.8 m=1 + +* Buffered with schmitt trigger buffer +Xtrig vcap vss vss vdd3v3 vdd3v3 out sky130_fd_sc_hvl__schmittbuf_1 + +* High voltage output (buffer) +Xbuf out vss vss vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8 + +* Level shift down (buffer) +Xlv1 out vss vss vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8 + +* Level shift down (inverter) +Xlv2 out vss vss vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8 + +* Fill cell +Xfill vss vss vdd3v3 vdd3v3 sky130_fd_sc_hvl__fill_4 + +* No tap cell in library? +* Xtap vdd3v3 vss sky130_fd_sc_hvl__tapvpwrvgnd_1 + +.ends + +.end
diff --git a/ngspice/simple_por/simple_por_tb.spice b/ngspice/simple_por/simple_por_tb.spice new file mode 100644 index 0000000..f982387 --- /dev/null +++ b/ngspice/simple_por/simple_por_tb.spice
@@ -0,0 +1,36 @@ +*------------------------------------------------------------------- +* Simple POR circuit for Caravel +*------------------------------------------------------------------- +* +* Architecture: see simple_por.spice +* Response of this circuit by ngspice simulation is a ~15ms delay. +*------------------------------------------------------------------- + +.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt +.include /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice +.include simple_por.spice + +*---------------------------- +* Testbench circuit +*---------------------------- +Vpwr vdda vss DC=0 PWL(0.0 0 100u 0 5m 3.3) +Vdig vccd vss DC=0 PWL(0.0 0 300u 0 5.3m 1.8) +Rgnd vss 0 0.01 +Cload1 porb_h vss 1E-12 +Cload2 por_l vss 1E-12 +Cload3 porb_l vss 1E-12 +Xpor vdda vccd vss porb_h por_l porb_l simple_por +*---------------------------- + +*---------------------------- +* Testbench control +*---------------------------- +.control +tran 10u 20m +plot porb_h +plot por_l +plot porb_l +.endc + +.end +
diff --git a/ngspice/simple_por/threshold_test_tb.spice b/ngspice/simple_por/threshold_test_tb.spice new file mode 100644 index 0000000..f7befa1 --- /dev/null +++ b/ngspice/simple_por/threshold_test_tb.spice
@@ -0,0 +1,32 @@ +*------------------------------------------------------------------- +* Threshold test for POR circuit +* Determine gate voltage at which the HV NFET draws 240nA nominal +* +* Result: 0.7575V +*------------------------------------------------------------------- + +.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt + + +*---------------------------- +* Testbench circuit +*---------------------------- +Rtest vdda mir1 1MEG +Xm1 mir1 vin vss vss sky130_fd_pr__nfet_g5v0d10v5 w=2 l=0.8 + +Vgate vin vss DC=0 +Vpwr vdda vss DC=3.3 +Rgnd vss 0 0.1 + +*---------------------------- +* Testbench control +*---------------------------- +.control +* DC sweep from 0.7 to 0.8V +dc Vgate 0.7 0.8 0.001 +wrdata test.data Vpwr#branch vin + +.endc + +.end +
diff --git a/qflow/README b/qflow/README new file mode 100644 index 0000000..f58340e --- /dev/null +++ b/qflow/README
@@ -0,0 +1,26 @@ +The qflow directory entries are only used to verify the all-digital frequency +locked loop circuit by running the verilog modules ring_osc2x13 and +digital_pll_controller seperately through synthesis. + +The ring_osc2x13 module is all gate-level except for a small amount of trivial +glue logic, so the fact that it is synthesized in qflow instead of openlane +(with a different setup passed to yosys) does not change the core part of the +ring oscillator that needs to be simulated. The synthesis results in a SPICE +netlist that can be simulated. + +For the digital_pll_controller, it is only needed to have a functional xspice +circuit of the digital part that can be used in the ngspice simulation. + +See the caravel/ngspice/digital_pll directory for the ngspice simulations. + +None of the files in this tree are used for the actual synthesis, placement, +and routing. The source files for qflow are pointers back to the verilog +module files in caravel/verilog/rtl/ directory. + +Qflow was only run through the "synthesis" stage to obtain the necessary +netlists. These can be recreated on demand from qflow, so the required +netlists were copied back to caravel/ngspice/digital_pll and the qflow +directory cleaned out. + +To reproduce the results, it is necessary to have the "tech" directory as a +symbolic link pointing to the open_pdks installation of sky130A.
diff --git a/qflow/digital_pll_controller/layout/.magicrc b/qflow/digital_pll_controller/layout/.magicrc new file mode 100644 index 0000000..122229c --- /dev/null +++ b/qflow/digital_pll_controller/layout/.magicrc
@@ -0,0 +1,75 @@ +puts stdout "Sourcing design .magicrc for technology sky130A ..." + +# Put grid on 0.005 pitch. This is important, as some commands don't +# rescale the grid automatically (such as lef read?). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 2} { + scalegrid 1 2 +} + +# drc off +drc euclidean on + +# Allow override of PDK path from environment variable PDKPATH +if {[catch {set PDKPATH $env(PDKPATH)}]} { + set PDKPATH "/home/tim/projects/efabless/tech/SW/sky130A" +} + +# loading technology +tech load $PDKPATH/libs.tech/magic/current/sky130A.tech + +# load device generator +source $PDKPATH/libs.tech/magic/current/sky130A.tcl + +# load bind keys (optional) +# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys + +# set units to lambda grid +snap lambda + +# set sky130 standard power, ground, and substrate names +set VDD VPWR +set GND VGND +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} { + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18 +} else { + addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE} +} + +# add path to GDS cells + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects}
diff --git a/qflow/digital_pll_controller/layout/.magicrc.orig b/qflow/digital_pll_controller/layout/.magicrc.orig new file mode 100644 index 0000000..122229c --- /dev/null +++ b/qflow/digital_pll_controller/layout/.magicrc.orig
@@ -0,0 +1,75 @@ +puts stdout "Sourcing design .magicrc for technology sky130A ..." + +# Put grid on 0.005 pitch. This is important, as some commands don't +# rescale the grid automatically (such as lef read?). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 2} { + scalegrid 1 2 +} + +# drc off +drc euclidean on + +# Allow override of PDK path from environment variable PDKPATH +if {[catch {set PDKPATH $env(PDKPATH)}]} { + set PDKPATH "/home/tim/projects/efabless/tech/SW/sky130A" +} + +# loading technology +tech load $PDKPATH/libs.tech/magic/current/sky130A.tech + +# load device generator +source $PDKPATH/libs.tech/magic/current/sky130A.tcl + +# load bind keys (optional) +# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys + +# set units to lambda grid +snap lambda + +# set sky130 standard power, ground, and substrate names +set VDD VPWR +set GND VGND +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} { + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18 +} else { + addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE} +} + +# add path to GDS cells + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects}
diff --git a/qflow/digital_pll_controller/layout/digital_pll_controller.par b/qflow/digital_pll_controller/layout/digital_pll_controller.par new file mode 100644 index 0000000..ce7c105 --- /dev/null +++ b/qflow/digital_pll_controller/layout/digital_pll_controller.par
@@ -0,0 +1,94 @@ +# sky130A.par --- Parameter file for GrayWolf +# NOTE: all distance units are in centimicrons unless otherwise stated +# WARNING: this is NOT tcl syntax! No Comments on end of actual data line. +# The vast majority of quantities here are not used (read instead from techLEF, etc.) + +RULES + # values are resistance in ohms/sq and capacitance in fF/um^2 + # TODO: properly pick directions + layer metal1 0.105 0.0001 horizontal + layer metal2 0.105 0.0001 vertical + layer metal3 0.105 0.0001 horizontal + layer metal4 0.105 0.0001 vertical + layer metal5 0.105 0.0001 horizontal + + via via12 metal1 metal2 + via via23 metal2 metal3 + via via34 metal3 metal4 + via via45 metal4 metal5 + + # 0.5 um + width metal1 50 + width metal2 60 + # 0.6 um + width metal3 60 + width metal4 60 + width metal5 60 + + # TODO verify these two numbers + width via12 50 + width via23 50 + width via34 50 + width via45 50 + + # Set spacing = track pitch - width, so that GrayWolf places pins + # on the right pitch. + # Pitches are (in um): + # metal1 = 200, metal2 = 160, metal3 = 200, metal4 = 320 +## pitch m1: 1.3um m2: 1.4um m3: 1.3um +## width m1: 0.5um m2: 0.6um m3: 0.6um +## space 0.8 0.8 0.7 (pitch calc) +## fab-space 0.45 0.5 0.6 + + spacing metal1 metal1 80 + spacing metal2 metal2 80 + spacing metal3 metal3 80 + spacing metal4 metal4 80 + spacing metal5 metal5 80 + + # (WAS:) Stacked vias allowed + # spacing via12 via23 0 + + # To disable Stacked?: give non-zero spacing (centimicrons = 10 nanometer = 1/100 of micron) + # TODO need real value here: + spacing via12 via23 0 + spacing via23 via34 0 + spacing via34 via45 0 + + # .2um .15um + overhang via12 metal1 20 + overhang via12 metal2 15 + + overhang via23 metal2 20 + overhang via23 metal3 15 + + overhang via34 metal3 14 + overhang via34 metal4 16 + overhang via45 metal4 14 + overhang via45 metal5 16 +ENDRULES + +*vertical_wire_weight : 1.0 +*vertical_path_weight : 1.0 +*padspacing : variable +*rowSep : 0.0 0 +# min pitch of m1,m2,m3 (FIXME): +*track.pitch : 130 +*graphics.wait : off +*last_chance.wait : off +*random.seed : 12345 +# TODO: proper track.pitch number above, plus feedThruWidth below + +TWMC*chip.aspect.ratio : 1.0 + +# FIXME: Change width to width of minimum fill cell +TWSC*feedThruWidth : 280 layer 1 +TWSC*do.global.route : on +TWSC*ignore_feeds : true +TWSC*call_row_evener : true +TWSC*even_rows_maximally : true +# TWSC*no.graphics : on + +GENR*row_to_tile_spacing: 1 +# GENR*numrows : 6 +GENR*flip_alternate_rows : 1
diff --git a/qflow/digital_pll_controller/log/qflow.log b/qflow/digital_pll_controller/log/qflow.log new file mode 100644 index 0000000..377c273 --- /dev/null +++ b/qflow/digital_pll_controller/log/qflow.log
@@ -0,0 +1 @@ +Starting new log file Tue Nov 24 20:34:58 2020
diff --git a/qflow/digital_pll_controller/project_vars.sh b/qflow/digital_pll_controller/project_vars.sh new file mode 100644 index 0000000..2fa3d92 --- /dev/null +++ b/qflow/digital_pll_controller/project_vars.sh
@@ -0,0 +1,66 @@ +#!/bin/tcsh -f +#------------------------------------------------------------ +# project variables for project ~/gits/caravel/qflow/digital_pll_controller +#------------------------------------------------------------ + +# Flow options: +# ------------------------------------------- +set synthesis_tool = yosys +set placement_tool = graywolf +set sta_tool = opensta +set router_tool = qrouter +set migrate_tool = magic_db +set lvs_tool = netgen_lvs +set drc_tool = magic_drc +set gds_tool = magic_gds +set display_tool = magic_view + +# Synthesis command options: +# ------------------------------------------- +# set hard_macros = +# set yosys_options = +# set yosys_script = +# set yosys_debug = +# set abc_script = +# set nobuffers = +# set inbuffers = +# set postproc_options = "-anchors" +# set xspice_options = "-io_time=500p -time=50p -idelay=5p -odelay=50p -cload=250f" +# set fill_ratios = "0,70,10,20" +# set nofanout = +# set fanout_options = "-l 200 -c 20" +# set source_file_list = +# set is_system_verilog = + +# Placement command options: +# ------------------------------------------- +# set initial_density = +# set graywolf_options = +set addspacers_options = "-stripe 2.5 50.0 PG" + +# Router command options: +# ------------------------------------------- +set route_show = 1 +# set route_layers = "5" +# set via_use = +# set via_stacks = +# set qrouter_options = +# set qrouter_nocleanup = + +# STA command options: +# ------------------------------------------- + +# Minimum period of the clock use "--period value" (value in ps) +# set opensta_options = +set vesta_options = "--long" + +# Other options: +# ------------------------------------------- +# set migrate_options = +# set lef_options = +# set drc_gdsview = +# set drc_options = +# set gds_options = + +#------------------------------------------------------------ +
diff --git a/qflow/digital_pll_controller/qflow_exec.sh b/qflow/digital_pll_controller/qflow_exec.sh new file mode 100755 index 0000000..3a547d6 --- /dev/null +++ b/qflow/digital_pll_controller/qflow_exec.sh
@@ -0,0 +1,17 @@ +#!/bin/tcsh -f +#------------------------------------------- +# qflow exec script for project ~/gits/caravel/qflow/digital_pll_controller +#------------------------------------------- + +# /usr/local/share/qflow/scripts/yosys.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller ~/gits/caravel/qflow/digital_pll_controller/source/digital_pll_controller.v || exit 1 +# /usr/local/share/qflow/scripts/graywolf.sh -d ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/opensta.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/qrouter.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/opensta.sh -d ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/magic_db.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/magic_drc.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/netgen_lvs.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/magic_gds.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/cleanup.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +/usr/local/share/qflow/scripts/cleanup.sh -p ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1 +# /usr/local/share/qflow/scripts/magic_view.sh ~/gits/caravel/qflow/digital_pll_controller digital_pll_controller || exit 1
diff --git a/qflow/digital_pll_controller/qflow_vars.sh b/qflow/digital_pll_controller/qflow_vars.sh new file mode 100644 index 0000000..1ff7b43 --- /dev/null +++ b/qflow/digital_pll_controller/qflow_vars.sh
@@ -0,0 +1,17 @@ +#!/bin/tcsh -f +#------------------------------------------- +# qflow variables for project ~/gits/caravel/qflow/digital_pll_controller +#------------------------------------------- + +set qflowversion=1.4.80 +set projectpath=~/gits/caravel/qflow/digital_pll_controller +set techdir=~/gits/caravel/qflow/digital_pll_controller/tech +set sourcedir=~/gits/caravel/qflow/digital_pll_controller/source +set synthdir=~/gits/caravel/qflow/digital_pll_controller/synthesis +set layoutdir=~/gits/caravel/qflow/digital_pll_controller/layout +set techname=sky130Ahd +set scriptdir=/usr/local/share/qflow/scripts +set bindir=/usr/local/share/qflow/bin +set logdir=~/gits/caravel/qflow/digital_pll_controller/log +#------------------------------------------- +
diff --git a/qflow/digital_pll_controller/source/digital_pll_controller.v b/qflow/digital_pll_controller/source/digital_pll_controller.v new file mode 120000 index 0000000..c9b260b --- /dev/null +++ b/qflow/digital_pll_controller/source/digital_pll_controller.v
@@ -0,0 +1 @@ +../../../verilog/rtl/digital_pll_controller.v \ No newline at end of file
diff --git a/qflow/digital_pll_controller/tech b/qflow/digital_pll_controller/tech new file mode 120000 index 0000000..b210657 --- /dev/null +++ b/qflow/digital_pll_controller/tech
@@ -0,0 +1 @@ +/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/qflow \ No newline at end of file
diff --git a/qflow/ring_osc2x13/layout/.magicrc b/qflow/ring_osc2x13/layout/.magicrc new file mode 100644 index 0000000..122229c --- /dev/null +++ b/qflow/ring_osc2x13/layout/.magicrc
@@ -0,0 +1,75 @@ +puts stdout "Sourcing design .magicrc for technology sky130A ..." + +# Put grid on 0.005 pitch. This is important, as some commands don't +# rescale the grid automatically (such as lef read?). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 2} { + scalegrid 1 2 +} + +# drc off +drc euclidean on + +# Allow override of PDK path from environment variable PDKPATH +if {[catch {set PDKPATH $env(PDKPATH)}]} { + set PDKPATH "/home/tim/projects/efabless/tech/SW/sky130A" +} + +# loading technology +tech load $PDKPATH/libs.tech/magic/current/sky130A.tech + +# load device generator +source $PDKPATH/libs.tech/magic/current/sky130A.tcl + +# load bind keys (optional) +# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys + +# set units to lambda grid +snap lambda + +# set sky130 standard power, ground, and substrate names +set VDD VPWR +set GND VGND +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} { + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18 +} else { + addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE} +} + +# add path to GDS cells + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects}
diff --git a/qflow/ring_osc2x13/layout/.magicrc.orig b/qflow/ring_osc2x13/layout/.magicrc.orig new file mode 100644 index 0000000..122229c --- /dev/null +++ b/qflow/ring_osc2x13/layout/.magicrc.orig
@@ -0,0 +1,75 @@ +puts stdout "Sourcing design .magicrc for technology sky130A ..." + +# Put grid on 0.005 pitch. This is important, as some commands don't +# rescale the grid automatically (such as lef read?). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 2} { + scalegrid 1 2 +} + +# drc off +drc euclidean on + +# Allow override of PDK path from environment variable PDKPATH +if {[catch {set PDKPATH $env(PDKPATH)}]} { + set PDKPATH "/home/tim/projects/efabless/tech/SW/sky130A" +} + +# loading technology +tech load $PDKPATH/libs.tech/magic/current/sky130A.tech + +# load device generator +source $PDKPATH/libs.tech/magic/current/sky130A.tcl + +# load bind keys (optional) +# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys + +# set units to lambda grid +snap lambda + +# set sky130 standard power, ground, and substrate names +set VDD VPWR +set GND VGND +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} { + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc + addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18 +} else { + addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE} + addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE} +} + +# add path to GDS cells + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects}
diff --git a/qflow/ring_osc2x13/layout/ring_osc2x13.par b/qflow/ring_osc2x13/layout/ring_osc2x13.par new file mode 100644 index 0000000..ce7c105 --- /dev/null +++ b/qflow/ring_osc2x13/layout/ring_osc2x13.par
@@ -0,0 +1,94 @@ +# sky130A.par --- Parameter file for GrayWolf +# NOTE: all distance units are in centimicrons unless otherwise stated +# WARNING: this is NOT tcl syntax! No Comments on end of actual data line. +# The vast majority of quantities here are not used (read instead from techLEF, etc.) + +RULES + # values are resistance in ohms/sq and capacitance in fF/um^2 + # TODO: properly pick directions + layer metal1 0.105 0.0001 horizontal + layer metal2 0.105 0.0001 vertical + layer metal3 0.105 0.0001 horizontal + layer metal4 0.105 0.0001 vertical + layer metal5 0.105 0.0001 horizontal + + via via12 metal1 metal2 + via via23 metal2 metal3 + via via34 metal3 metal4 + via via45 metal4 metal5 + + # 0.5 um + width metal1 50 + width metal2 60 + # 0.6 um + width metal3 60 + width metal4 60 + width metal5 60 + + # TODO verify these two numbers + width via12 50 + width via23 50 + width via34 50 + width via45 50 + + # Set spacing = track pitch - width, so that GrayWolf places pins + # on the right pitch. + # Pitches are (in um): + # metal1 = 200, metal2 = 160, metal3 = 200, metal4 = 320 +## pitch m1: 1.3um m2: 1.4um m3: 1.3um +## width m1: 0.5um m2: 0.6um m3: 0.6um +## space 0.8 0.8 0.7 (pitch calc) +## fab-space 0.45 0.5 0.6 + + spacing metal1 metal1 80 + spacing metal2 metal2 80 + spacing metal3 metal3 80 + spacing metal4 metal4 80 + spacing metal5 metal5 80 + + # (WAS:) Stacked vias allowed + # spacing via12 via23 0 + + # To disable Stacked?: give non-zero spacing (centimicrons = 10 nanometer = 1/100 of micron) + # TODO need real value here: + spacing via12 via23 0 + spacing via23 via34 0 + spacing via34 via45 0 + + # .2um .15um + overhang via12 metal1 20 + overhang via12 metal2 15 + + overhang via23 metal2 20 + overhang via23 metal3 15 + + overhang via34 metal3 14 + overhang via34 metal4 16 + overhang via45 metal4 14 + overhang via45 metal5 16 +ENDRULES + +*vertical_wire_weight : 1.0 +*vertical_path_weight : 1.0 +*padspacing : variable +*rowSep : 0.0 0 +# min pitch of m1,m2,m3 (FIXME): +*track.pitch : 130 +*graphics.wait : off +*last_chance.wait : off +*random.seed : 12345 +# TODO: proper track.pitch number above, plus feedThruWidth below + +TWMC*chip.aspect.ratio : 1.0 + +# FIXME: Change width to width of minimum fill cell +TWSC*feedThruWidth : 280 layer 1 +TWSC*do.global.route : on +TWSC*ignore_feeds : true +TWSC*call_row_evener : true +TWSC*even_rows_maximally : true +# TWSC*no.graphics : on + +GENR*row_to_tile_spacing: 1 +# GENR*numrows : 6 +GENR*flip_alternate_rows : 1
diff --git a/qflow/ring_osc2x13/log/qflow.log b/qflow/ring_osc2x13/log/qflow.log new file mode 100644 index 0000000..be8f5fe --- /dev/null +++ b/qflow/ring_osc2x13/log/qflow.log
@@ -0,0 +1 @@ +Starting new log file Tue Nov 24 20:36:00 2020
diff --git a/qflow/ring_osc2x13/project_vars.sh b/qflow/ring_osc2x13/project_vars.sh new file mode 100644 index 0000000..5010715 --- /dev/null +++ b/qflow/ring_osc2x13/project_vars.sh
@@ -0,0 +1,66 @@ +#!/bin/tcsh -f +#------------------------------------------------------------ +# project variables for project ~/gits/caravel/qflow/ring_osc2x13 +#------------------------------------------------------------ + +# Flow options: +# ------------------------------------------- +# set synthesis_tool = yosys +# set placement_tool = graywolf +# set sta_tool = vesta +# set router_tool = qrouter +# set migrate_tool = magic_db +# set lvs_tool = netgen_lvs +# set drc_tool = magic_drc +# set gds_tool = magic_gds +# set display_tool = magic_view + +# Synthesis command options: +# ------------------------------------------- +# set hard_macros = +# set yosys_options = +# set yosys_script = +# set yosys_debug = +# set abc_script = +# set nobuffers = +# set inbuffers = +# set postproc_options = "-anchors" +# set xspice_options = "-io_time=500p -time=50p -idelay=5p -odelay=50p -cload=250f" +# set fill_ratios = "0,70,10,20" +# set nofanout = +# set fanout_options = "-l 200 -c 20" +# set source_file_list = +# set is_system_verilog = + +# Placement command options: +# ------------------------------------------- +# set initial_density = +# set graywolf_options = +# set addspacers_options = "-stripe 2.5 50.0 PG" + +# Router command options: +# ------------------------------------------- +# set route_show = +# set route_layers = "5" +# set via_use = +# set via_stacks = +# set qrouter_options = +# set qrouter_nocleanup = + +# STA command options: +# ------------------------------------------- + +# Minimum period of the clock use "--period value" (value in ps) +# set opensta_options = +# set vesta_options = + +# Other options: +# ------------------------------------------- +# set migrate_options = +# set lef_options = +# set drc_gdsview = +# set drc_options = +# set gds_options = + +#------------------------------------------------------------ +
diff --git a/qflow/ring_osc2x13/qflow_exec.sh b/qflow/ring_osc2x13/qflow_exec.sh new file mode 100755 index 0000000..e45d63b --- /dev/null +++ b/qflow/ring_osc2x13/qflow_exec.sh
@@ -0,0 +1,17 @@ +#!/bin/tcsh -f +#------------------------------------------- +# qflow exec script for project ~/gits/caravel/qflow/ring_osc2x13 +#------------------------------------------- + +# /usr/local/share/qflow/scripts/yosys.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 ~/gits/caravel/qflow/ring_osc2x13/source/ring_osc2x13.v || exit 1 +# /usr/local/share/qflow/scripts/graywolf.sh -d ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/vesta.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/qrouter.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/vesta.sh -d ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/magic_db.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/magic_drc.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/netgen_lvs.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/magic_gds.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/cleanup.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +/usr/local/share/qflow/scripts/cleanup.sh -p ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1 +# /usr/local/share/qflow/scripts/magic_view.sh ~/gits/caravel/qflow/ring_osc2x13 ring_osc2x13 || exit 1
diff --git a/qflow/ring_osc2x13/qflow_vars.sh b/qflow/ring_osc2x13/qflow_vars.sh new file mode 100644 index 0000000..cb887d8 --- /dev/null +++ b/qflow/ring_osc2x13/qflow_vars.sh
@@ -0,0 +1,17 @@ +#!/bin/tcsh -f +#------------------------------------------- +# qflow variables for project ~/gits/caravel/qflow/ring_osc2x13 +#------------------------------------------- + +set qflowversion=1.4.80 +set projectpath=~/gits/caravel/qflow/ring_osc2x13 +set techdir=~/gits/caravel/qflow/ring_osc2x13/tech +set sourcedir=~/gits/caravel/qflow/ring_osc2x13/source +set synthdir=~/gits/caravel/qflow/ring_osc2x13/synthesis +set layoutdir=~/gits/caravel/qflow/ring_osc2x13/layout +set techname=sky130Ahd +set scriptdir=/usr/local/share/qflow/scripts +set bindir=/usr/local/share/qflow/bin +set logdir=~/gits/caravel/qflow/ring_osc2x13/log +#------------------------------------------- +
diff --git a/qflow/ring_osc2x13/source/ring_osc2x13.v b/qflow/ring_osc2x13/source/ring_osc2x13.v new file mode 120000 index 0000000..c8a27c4 --- /dev/null +++ b/qflow/ring_osc2x13/source/ring_osc2x13.v
@@ -0,0 +1 @@ +../../../verilog/rtl/ring_osc2x13.v \ No newline at end of file
diff --git a/qflow/ring_osc2x13/tech b/qflow/ring_osc2x13/tech new file mode 120000 index 0000000..b210657 --- /dev/null +++ b/qflow/ring_osc2x13/tech
@@ -0,0 +1 @@ +/home/tim/projects/efabless/tech/SW/sky130A/libs.tech/qflow \ No newline at end of file
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile index f8905a2..305375f 100644 --- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile +++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile index 7ebd3aa..9ba4635 100644 --- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile +++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -25,7 +25,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile index 3b1e137..0bcd880 100644 --- a/verilog/dv/caravel/mgmt_soc/mem/Makefile +++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile index 3713d77..d477f20 100644 --- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile +++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -25,7 +25,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile index 33fffa3..92919b5 100644 --- a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile +++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
@@ -25,7 +25,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile index 3cbea19..1fdfeae 100644 --- a/verilog/dv/caravel/mgmt_soc/perf/Makefile +++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile index f94b34f..4750a33 100644 --- a/verilog/dv/caravel/mgmt_soc/pll/Makefile +++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/mgmt_soc/storage/Makefile index 5d9e313..2792ce9 100644 --- a/verilog/dv/caravel/mgmt_soc/storage/Makefile +++ b/verilog/dv/caravel/mgmt_soc/storage/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile index ebd6b45..0cd4654 100644 --- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile +++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile index a8439b4..92e809f 100644 --- a/verilog/dv/caravel/mgmt_soc/timer/Makefile +++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile index 6b1bbd9..73cecf5 100644 --- a/verilog/dv/caravel/mgmt_soc/timer2/Makefile +++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
@@ -16,7 +16,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -Wall -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ @@ -24,7 +24,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile index 1433f85..004a876 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/Makefile +++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -25,7 +25,7 @@ vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile index 52617aa..3ab6272 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile +++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -18,13 +18,13 @@ %.vvp: %_tb.v %.hex iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ - $< -o $@ + -o $@ $< %.vcd: %.vvp vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v index 153e704..63b7c93 100644 --- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v +++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -86,20 +86,16 @@ #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); end - wire flash_csb; + wire flash_csb; wire flash_clk; wire flash_io0; wire flash_io1; - wire VDD1V8; - wire VDD3V3; - wire VSS; - - assign VDD3V3 = power1; - assign VDD1V8 = power2; - assign USER_VDD3V3 = power3; - assign USER_VDD1V8 = power4; - assign VSS = 1'b0; + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; caravel uut ( .vddio (VDD3V3),
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/la_test1/Makefile index cc8f204..19fd4a1 100644 --- a/verilog/dv/caravel/user_proj_example/la_test1/Makefile +++ b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
@@ -18,13 +18,13 @@ %.vvp: %_tb.v %.hex iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ - $< -o $@ + -o $@ $< %.vcd: %.vvp vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile index 12871dd..d9d9a0d 100644 --- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile +++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
@@ -18,21 +18,21 @@ %.vvp: %_tb.v %.hex iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ - $< -o $@ + -o $@ $< %.vcd: %.vvp vvp $< %.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s - ${GCC_PATH}/${GCC_PREFIX}-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-unknown-elf-objcopy -O verilog $< $@ + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -i 's/@10000000/@00000000/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 95ca327..130a35c 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v
@@ -35,6 +35,7 @@ `include "caravel_clocking.v" `include "mgmt_core.v" `include "mgmt_protect.v" +`include "mgmt_protect_hv.v" `include "mprj_io.v" `include "chip_io.v" `include "user_id_programming.v" @@ -293,12 +294,13 @@ wire [7:0] spi_ro_config_core; // LA signals - wire [127:0] la_output_core; // From CPU to MPRJ - wire [127:0] la_data_in_mprj; // From CPU to MPRJ + wire [127:0] la_data_in_user; // From CPU to MPRJ + wire [127:0] la_data_in_mprj; // From MPRJ to CPU wire [127:0] la_data_out_mprj; // From CPU to MPRJ - wire [127:0] la_output_mprj; // From MPRJ to CPU - wire [127:0] la_oen; // LA output enable from CPU perspective (active-low) - + wire [127:0] la_data_out_user; // From MPRJ to CPU + wire [127:0] la_oen_user; // From CPU to MPRJ + wire [127:0] la_oen_mprj; // From CPU to MPRJ + // WB MI A (User Project) wire mprj_cyc_o_core; wire mprj_stb_o_core; @@ -386,9 +388,9 @@ .user_clk(caravel_clk2), .core_rstn(caravel_rstn), // Logic Analyzer - .la_input(la_data_out_mprj), - .la_output(la_output_core), - .la_oen(la_oen), + .la_input(la_data_in_mprj), + .la_output(la_data_out_mprj), + .la_oen(la_oen_mprj), // User Project IO Control .mprj_vcc_pwrgood(mprj_vcc_pwrgood), .mprj2_vcc_pwrgood(mprj2_vcc_pwrgood), @@ -452,8 +454,12 @@ .mprj_sel_o_core(mprj_sel_o_core), .mprj_adr_o_core(mprj_adr_o_core), .mprj_dat_o_core(mprj_dat_o_core), - .la_output_core(la_output_core), - .la_oen(la_oen), + .la_data_out_core(la_data_out_user), + .la_data_out_mprj(la_data_out_mprj), + .la_data_in_core(la_data_in_user), + .la_data_in_mprj(la_data_in_mprj), + .la_oen_mprj(la_oen_mprj), + .la_oen_core(la_oen_user), .user_clock(mprj_clock), .user_clock2(mprj_clock2), @@ -465,7 +471,6 @@ .mprj_sel_o_user(mprj_sel_o_user), .mprj_adr_o_user(mprj_adr_o_user), .mprj_dat_o_user(mprj_dat_o_user), - .la_data_in_mprj(la_data_in_mprj), .user1_vcc_powergood(mprj_vcc_pwrgood), .user2_vcc_powergood(mprj2_vcc_pwrgood), .user1_vdd_powergood(mprj_vdd_pwrgood), @@ -499,9 +504,9 @@ .wbs_ack_o(mprj_ack_i_core), .wbs_dat_o(mprj_dat_i_core), // Logic Analyzer - .la_data_in(la_data_in_mprj), - .la_data_out(la_data_out_mprj), - .la_oen (la_oen), + .la_data_in(la_data_in_user), + .la_data_out(la_data_out_user), + .la_oen(la_oen_user), // IO Pads .io_in (user_io_in), .io_out(user_io_out),
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v index ad25704..d285a91 100644 --- a/verilog/rtl/mgmt_protect.v +++ b/verilog/rtl/mgmt_protect.v
@@ -35,8 +35,17 @@ input [3:0] mprj_sel_o_core, input [31:0] mprj_adr_o_core, input [31:0] mprj_dat_o_core, - input [127:0] la_output_core, - input [127:0] la_oen, + + // All signal in/out directions are the reverse of the signal + // names at the buffer intrface. + + output [127:0] la_data_in_mprj, + input [127:0] la_data_out_mprj, + input [127:0] la_oen_mprj, + + input [127:0] la_data_out_core, + output [127:0] la_data_in_core, + output [127:0] la_oen_core, output user_clock, output user_clock2, @@ -48,15 +57,14 @@ output [3:0] mprj_sel_o_user, output [31:0] mprj_adr_o_user, output [31:0] mprj_dat_o_user, - output [127:0] la_data_in_mprj, output user1_vcc_powergood, output user2_vcc_powergood, output user1_vdd_powergood, output user2_vdd_powergood ); - wire [74:0] mprj_logic1; - wire mprj2_logic1; + wire [458:0] mprj_logic1; + wire mprj2_logic1; wire mprj_vdd_logic1_h; wire mprj2_vdd_logic1_h; @@ -68,7 +76,9 @@ wire user1_vdd_powergood; wire user2_vdd_powergood; - sky130_fd_sc_hd__conb_1 mprj_logic_high [74:0] ( + wire [127:0] la_data_in_mprj_bar; + + sky130_fd_sc_hd__conb_1 mprj_logic_high [458:0] ( `ifdef USE_POWER_PINS .VPWR(vccd1), .VGND(vssd1), @@ -92,54 +102,55 @@ // Logic high in the VDDA (3.3V) domains - sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl ( + mgmt_protect_hv powergood_check ( `ifdef USE_POWER_PINS - .VPWR(vdda1), - .VGND(vssa1), - .VPB(vdda1), - .VNB(vssa1), + .vccd(vccd), + .vssd(vssd), + .vdda1(vdda1), + .vssa1(vssa1), + .vdda2(vdda2), + .vssa2(vssa2), `endif - .HI(mprj_vdd_logic1_h), - .LO() - ); - - sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl ( -`ifdef USE_POWER_PINS - .VPWR(vdda2), - .VGND(vssa2), - .VPB(vdda2), - .VNB(vssa2), -`endif - .HI(mprj2_vdd_logic1_h), - .LO() - ); - - // Level shift the logic high signals into the 1.8V domain - - sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv ( -`ifdef USE_POWER_PINS - .VPWR(vdda1), - .VGND(vssd), - .LVPWR(vccd), - .VPB(vdda1), - .VNB(vssd), -`endif - .X(mprj_vdd_logic1), - .A(mprj_vdd_logic1_h) + .mprj_vdd_logic1(mprj_vdd_logic1), + .mprj2_vdd_logic1(mprj2_vdd_logic1) ); - sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv ( + + // Buffering from the user side to the management side. + // NOTE: This is intended to be better protected, by a full + // chain of an lv-to-hv buffer followed by an hv-to-lv buffer. + // This serves as a placeholder until that configuration is + // checked and characterized. The function below forces the + // data input to the management core to be a solid logic 0 when + // the user project is powered down. + + sky130_fd_sc_hd__nand2_4 user_to_mprj_in_gates [127:0] ( `ifdef USE_POWER_PINS - .VPWR(vdda2), - .VGND(vssd), - .LVPWR(vccd), - .VPB(vdda2), - .VNB(vssd), + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), `endif - .X(mprj2_vdd_logic1), - .A(mprj2_vdd_logic1_h) + .Y(la_data_in_mprj_bar), + .A(la_data_out_core), + .B(mprj_logic1[457:330]) ); + sky130_fd_sc_hd__inv_8 user_to_mprj_in_buffers [127:0] ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .Y(la_data_in_mprj), + .A(la_data_in_mprj_bar) + ); + + // The remaining circuitry guards against the management + // SoC dumping current into the user project area when + // the user project area is powered down. + sky130_fd_sc_hd__einvp_8 mprj_rstn_buf ( `ifdef USE_POWER_PINS .VPWR(vccd), @@ -250,11 +261,8 @@ .TE(mprj_logic1[73:42]) ); - /* The LA buffers are controlled from the user side, so */ - /* it is only necessary to make sure that the function */ - /* is inverting the OEB signal and using positive-sense */ - /* enable, so that the buffer is disabled on user-side */ - /* power-down of vccd1. */ + /* Project data out from the managment side to the user project */ + /* area when the user project is powered down. */ sky130_fd_sc_hd__einvp_8 la_buf [127:0] ( `ifdef USE_POWER_PINS @@ -263,11 +271,26 @@ .VPB(vccd), .VNB(vssd), `endif - .Z(la_data_in_mprj), - .A(~la_output_core), - .TE(~la_oen) + .Z(la_data_in_core), + .A(~la_data_out_mprj), + .TE(mprj_logic1[201:74]) ); + /* Project data out enable (bar) from the managment side to the */ + /* user project area when the user project is powered down. */ + + sky130_fd_sc_hd__einvp_8 user_to_mprj_oen_buffers [127:0] ( +`ifdef USE_POWER_PINS + .VPWR(vccd), + .VGND(vssd), + .VPB(vccd), + .VNB(vssd), +`endif + .Z(la_oen_core), + .A(~la_oen_mprj), + .TE(mprj_logic1[329:202]) + ); + /* The conb cell output is a resistive connection directly to */ /* the power supply, so when returning the user1_powergood */ /* signal, make sure that it is buffered properly. */ @@ -279,7 +302,7 @@ .VPB(vccd), .VNB(vssd), `endif - .A(mprj_logic1[74]), + .A(mprj_logic1[458]), .X(user1_vcc_powergood) ); @@ -290,7 +313,7 @@ .VPB(vccd), .VNB(vssd), `endif - .A(mprj2_logic1), + .A(mprj2_vdd_logic1), .X(user2_vcc_powergood) );
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v new file mode 100644 index 0000000..9c8cabe --- /dev/null +++ b/verilog/rtl/mgmt_protect_hv.v
@@ -0,0 +1,79 @@ +`default_nettype none +/*----------------------------------------------------------------------*/ +/* mgmt_protect_hv: */ +/* */ +/* High voltage (3.3V) part of the mgmt_protect module. Split out into */ +/* a separate module and file so that the synthesis tools can handle it */ +/* separately from the rest, since it uses a different standard cell */ +/* library. See the file mgmt_protect.v for a full description of the */ +/* whole management protection method. */ +/*----------------------------------------------------------------------*/ + +module mgmt_protect_hv ( + inout vccd, + inout vssd, + inout vdda1, + inout vssa1, + inout vdda2, + inout vssa2, + + output mprj_vdd_logic1, + output mprj2_vdd_logic1 + +); + + wire mprj_vdd_logic1_h; + wire mprj2_vdd_logic1_h; + + // Logic high in the VDDA (3.3V) domains + + sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl ( +`ifdef USE_POWER_PINS + .VPWR(vdda1), + .VGND(vssa1), + .VPB(vdda1), + .VNB(vssa1), +`endif + .HI(mprj_vdd_logic1_h), + .LO() + ); + + sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl ( +`ifdef USE_POWER_PINS + .VPWR(vdda2), + .VGND(vssa2), + .VPB(vdda2), + .VNB(vssa2), +`endif + .HI(mprj2_vdd_logic1_h), + .LO() + ); + + // Level shift the logic high signals into the 1.8V domain + + sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv ( +`ifdef USE_POWER_PINS + .VPWR(vdda1), + .VGND(vssd), + .LVPWR(vccd), + .VPB(vdda1), + .VNB(vssd), +`endif + .X(mprj_vdd_logic1), + .A(mprj_vdd_logic1_h) + ); + + sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv ( +`ifdef USE_POWER_PINS + .VPWR(vdda2), + .VGND(vssd), + .LVPWR(vccd), + .VPB(vdda2), + .VNB(vssd), +`endif + .X(mprj2_vdd_logic1), + .A(mprj2_vdd_logic1_h) + ); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v index 6307e79..f04fa5c 100644 --- a/verilog/rtl/simple_por.v +++ b/verilog/rtl/simple_por.v
@@ -22,7 +22,8 @@ end // Emulate current source on capacitor as a 500ns delay either up or - // down. + // down. Note that this is sped way up for verilog simulation; the + // actual circuit is set to a 15ms delay. always @(posedge vdd3v3) begin #500 inode <= 1'b1;