| commit | bd226983868eda52515b6cb5247c66b205ff8c75 | [log] [tgz] |
|---|---|---|
| author | Jecel Assumpcao Jr <jecel@merlintec.com> | Sun Nov 29 15:42:03 2020 -0300 |
| committer | Jecel Assumpcao Jr <jecel@merlintec.com> | Sun Nov 29 15:42:03 2020 -0300 |
| tree | 33e9a91bd4b58e18f7c0b42dd6337571dc1b1e16 | |
| parent | 1976a03333df91603f99bfc2037cbee488f83cbc [diff] |
added labels to generator loops since Quartus demands them
This is a combination of the Morphle Logic asynchronous runtime reconfigurable array with the Caravel project to design a chip for the Skywater 130 nm technology.
README for Morphle Logic gives more details about that part of the project.
This version of the chip uses a single block of “yellow cells” from Morphle Logic connected to the logic analyzer pins inside Caravel. The processor in the management frame can inject a configuration into the block (a reset, configuration clock and 16 configuration bits interface with the capability of reading back 16 configuration bits coming out of the bottom of the block) and then inject a value into the top interface of the block (16 pairs of bits) and read back the value coming out the top of the block. The left, down and right interfaces are hardwired to loop back into themselves (which shouldn't matter as their missing neighbors always assert that they are “empty”).
Start by cloning the repo and uncompressing the files.
git clone https://github.com/efabless/caravel.git cd caravel make uncompress
Install the required version of the PDK by running the following commands:
export PDK_ROOT=<The place where you want to install the pdk> make pdk
Then, you can learn more about the caravel chip by watching these video:
Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
If you will use OpenLANE to harden your design, go through the instructions in this README.md.
Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
./gds/ in the Caravel directory.Run the following command:
export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step> make
This should merge the GDSes using magic and you'll end up with your version of ./gds/caravel.gds. You should expect hundred of thousands of magic DRC violations with the current “development” state of caravel.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample user project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: