(1) Added a wrapper interface between the top level verilog and the user project
example.
(2) Corrected broken directory references in README.md
(3) Added the caravel.pdf document (first draft, mostly just figures and no text).
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 100644
index 0000000..8b143db
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,102 @@
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter IO_PADS = 37,
+ parameter PWR_PADS = 4,
+ parameter BITS = 32
+)(
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oen,
+
+ // IOs
+ input [IO_PADS-1:0] io_in,
+ output [IO_PADS-1:0] io_out,
+ output [IO_PADS-1:0] io_oeb,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2
+);
+
+ /*--------------------------------------*/
+ /* User project is instantiated here */
+ /*--------------------------------------*/
+
+ user_proj_example #(
+ .IO_PADS(`MPRJ_IO_PADS),
+ .PWR_PADS(`MPRJ_PWR_PADS)
+ ) mprj (
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+
+ // MGMT core clock and reset
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oen (la_oen),
+
+ // IO Pads
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb)
+ );
+
+endmodule // user_project_wrapper
