| commit | a922b7ca69da6c7be13f60331348aae6e343e545 | [log] [tgz] |
|---|---|---|
| author | Manar <manarabdelatty@aucegypt.edu> | Wed Oct 28 22:24:06 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Wed Oct 28 22:58:30 2020 +0200 |
| tree | 88b6b8cd5099a692f6e03717dbdb8cbbea62b3b5 | |
| parent | 206b57588c1914a39aa9ba06e26d3011a383b536 [diff] [blame] |
Removed storage area from mgmt_core - commented USE_OPENRAM in defines.v to use 1kb of synthesized memory
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v index 5cc6d03..e2f457a 100644 --- a/verilog/rtl/defines.v +++ b/verilog/rtl/defines.v
@@ -4,8 +4,7 @@ `define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */ // Size of soc_mem_synth -`define MEM_SYNTH_WORDS 1024 // Type and size of soc_mem -`define USE_OPENRAM +// `define USE_OPENRAM `define MEM_WORDS 256