| commit | a4367b33414c8f1089c3ef9a2f906b5909e28533 | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Thu Nov 26 21:03:30 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Thu Nov 26 21:03:30 2020 +0200 |
| tree | d102ed881e476f5ded60bab9501fa34d97bd898f | |
| parent | fe9c3bb707a0e10e9b31adc0352bce2ffaa494cb [diff] |
Update wrapper, add obstructed version - pins are now a bit wider and extend slightly outside the core area - added an obstructed version of the wrapper to be used for routing to gurantee that none of the resources within the user area is taken while top-level-routing - the core ring is completely outside the project area as marked by the boundary in the various views (TODO: resolve FastRoute issue with non-zero origins)
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
Start by cloning the repo and uncompressing the files.
git clone https://github.com/efabless/caravel.git cd caravel make uncompress
Then, you can learn more about the caravel chip by watching these video:
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: