| commit | 9c822c61eb0ee1e4c405a659421ee914e153ec52 | [log] [tgz] |
|---|---|---|
| author | R. Timothy Edwards <tim@opencircuitdesign.com> | Mon Nov 09 09:43:04 2020 -0500 |
| committer | GitHub <noreply@github.com> | Mon Nov 09 09:43:04 2020 -0500 |
| tree | 81726c3a9b9cc02a56fdf148c8982a0bcf266884 | |
| parent | 009f0d4d391b3b222c7a0474b35405c695b67bcc [diff] | |
| parent | 60a03727f7c54c1478b8f945de5e4b20b321a0c9 [diff] |
Merge pull request #33 from Manarabdelaty/custom_mem Added power pins to the custom memory cells
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index a72d99e..f1feed5 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -91,7 +91,7 @@ ) counter( .clk(clk), .reset(rst), - .ready(wbs_ack_i), + .ready(wbs_ack_o), .valid(valid), .rdata(rdata), .wdata(wbs_dat_i),