Merge pull request #33 from Manarabdelaty/custom_mem

Added power pins to the custom memory cells

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index a72d99e..f1feed5 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -91,7 +91,7 @@
     ) counter(
         .clk(clk),
         .reset(rst),
-        .ready(wbs_ack_i),
+        .ready(wbs_ack_o),
         .valid(valid),
         .rdata(rdata),
         .wdata(wbs_dat_i),