commit | 86ec7cde98889c55aa77e10428cee91564770511 | [log] [tgz] |
---|---|---|
author | Matt Venn <matt@mattvenn.net> | Mon Nov 16 12:01:14 2020 +0100 |
committer | Matt Venn <matt@mattvenn.net> | Mon Nov 16 12:01:14 2020 +0100 |
tree | ed5d102ae14d7dca40e78ce0ae9a81ec0548cfd8 | |
parent | 1a146db84930db7f1e201e7abb553c9361f89bfb [diff] [blame] |
add default nettype none
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v index 1397cd4..7d9ddb1 100644 --- a/verilog/rtl/wb_intercon.v +++ b/verilog/rtl/wb_intercon.v
@@ -1,3 +1,4 @@ +`default_nettype none module wb_intercon #( parameter DW = 32, // Data Width parameter AW = 32, // Address Width