commit 64c17e8f8e46c20e6ac8f4f792bea8b922acabe9
author Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Nov 18 20:17:26 2020 +0200
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Nov 18 20:17:26 2020 +0200
tree 7b220d57a07ee7474e5ee1e7403c17e5d1f608b7
parent 69663c76d6f4b937374642818956e4b6ca8dabed

Add missing USE_POWER_PINS in other modules

verilog/rtl/user_id_programming.v

diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index d3186c1..421e663 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -18,10 +18,12 @@
     // For the mask revision input, use an array of digital constant logic cells
 
     sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
+`ifdef USE_POWER_PINS
             .VPWR(vdd1v8),
             .VPB(vdd1v8),
             .VNB(vss),
             .VGND(vss),
+`endif
             .HI(user_proj_id_high),
             .LO(user_proj_id_low)
     );