commit 589a528c7eec14294621d99747bb0850dcfae114
author manarabdelaty <manarabdelatty@aucegypt.edu> Sat Dec 05 01:06:48 2020 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Sat Dec 05 01:06:48 2020 +0200
tree 64a4cc6b3d0f53e1ccfdff6560449668d7b995fc
parent ea96b3a6c6fa5e4c7236be9292cda5f9774c128f

RTL updates to fix gl sim

verilog/rtl/gpio_control_block.v

diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 8ccdfdd..9f9ac7a 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -38,8 +38,8 @@
     parameter TRIP_INIT = 1'b0,
     parameter IB_INIT = 1'b0,
     parameter IENB_INIT = 1'b0,
-    parameter OENB_INIT = 1'b1,
-    parameter DM_INIT = 3'b001,
+    parameter OENB_INIT = `OENB_INIT,
+    parameter DM_INIT = `DM_INIT,
     parameter AENA_INIT = 1'b0,
     parameter ASEL_INIT = 1'b0,
     parameter APOL_INIT = 1'b0