Verilog Library of building blocks for Morphle Logic

ycell.v

The basic element is ycell (“yellow cell”, named so because of the first illustrations). This file also defines a trivial configuration circuit that shifts in 3 configuration bits and decodes the 8 possible combinations into the needed control signals.

yblock.v

yblock just being an array of ycells of the specified BLOCKWIDTH and BLOCKHEIGHT. Besides connecting the ycells to each other, yblock connects the wires at the edges of the array to ports so it can be used as a component in a larger system.

Caravel User Project Examples

user_proj_block.v