Update mgmt_protect & co. openlane configs
diff --git a/openlane/mgmt_protect/config.tcl b/openlane/mgmt_protect/config.tcl
index f0b1e80..6464dd4 100755
--- a/openlane/mgmt_protect/config.tcl
+++ b/openlane/mgmt_protect/config.tcl
@@ -22,18 +22,22 @@
$script_dir/../../verilog/rtl/mgmt_protect.v"
set ::env(VERILOG_FILES_BLACKBOX) "\
+ $script_dir/../../verilog/rtl/mprj_logic_high.v\
+ $script_dir/../../verilog/rtl/mprj2_logic_high.v\
$script_dir/../../verilog/rtl/mgmt_protect_hv.v"
set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/mprj_logic_high.lef\
+ $script_dir/../../lef/mprj2_logic_high.lef\
$script_dir/../../lef/mgmt_protect_hv.lef"
set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/mprj_logic_high.gds\
+ $script_dir/../../gds/mprj2_logic_high.gds\
$script_dir/../../gds/mgmt_protect_hv.gds"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-# there is $not...
-# set ::env(SYNTH_TOP_LEVEL) 1
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -41,7 +45,7 @@
# set ::env(FP_CONTEXT_LEF) $script_dir/../caravel/runs/caravel/tmp/merged_unpadded.lef
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 55"
+set ::env(DIE_AREA) "0 0 1000 90"
set ::env(BOTTOM_MARGIN_MULT) 2
set ::env(TOP_MARGIN_MULT) 2
set ::env(LEFT_MARGIN_MULT) 12
@@ -50,6 +54,7 @@
set ::env(FP_IO_VEXTEND) 2
set ::env(FP_IO_HEXTEND) 2
+set ::env(CELL_PAD) 0
set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_PDN_AUTO_ADJUST) 0
@@ -62,20 +67,21 @@
set ::env(FP_PDN_CORE_RING_HWIDTH) 0.3
set ::env(FP_PDN_CORE_RING_VOFFSET) 7
set ::env(FP_PDN_CORE_RING_HOFFSET) 7
-set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_VWIDTH) 1.2
set ::env(FP_PDN_HWIDTH) 0.3
-set ::env(FP_PDN_VPITCH) 200
+set ::env(FP_PDN_VPITCH) 150
set ::env(FP_PDN_HPITCH) 5.44
+set ::env(FP_PDN_VSPACING) 3.2
set ::env(FP_PDN_LOWER_LAYER) met4
set ::env(FP_PDN_UPPER_LAYER) met3
set ::env(GLB_RT_MAXLAYER) 5
set ::env(GLB_RT_OBS) "met5 $::env(DIE_AREA)"
-set ::env(FP_VERTICAL_HALO) 0
+set ::env(FP_VERTICAL_HALO) 3
-set ::env(PL_TARGET_DENSITY) 0.55
+set ::env(PL_TARGET_DENSITY) 0.3
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-set ::env(DIODE_INSERTION_STRATEGY) 3
+# set ::env(GLB_RT_ALLOW_CONGESTION) 1
+set ::env(DIODE_INSERTION_STRATEGY) 1
diff --git a/openlane/mgmt_protect/macro_placement.cfg b/openlane/mgmt_protect/macro_placement.cfg
index efae4a1..720217a 100644
--- a/openlane/mgmt_protect/macro_placement.cfg
+++ b/openlane/mgmt_protect/macro_placement.cfg
@@ -1 +1,3 @@
-powergood_check 783.050 15.180 N
+powergood_check 657.050 10.92 N
+mprj_logic_high_inst 306.38 46.84 N
+mprj2_logic_high_inst 152.630 11.12 N
diff --git a/openlane/mgmt_protect_hv/config.tcl b/openlane/mgmt_protect_hv/config.tcl
index b151739..5956d84 100644
--- a/openlane/mgmt_protect_hv/config.tcl
+++ b/openlane/mgmt_protect_hv/config.tcl
@@ -22,8 +22,17 @@
set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_LOWER_LAYER) met2
set ::env(FP_PDN_UPPER_LAYER) met3
+set ::env(FP_PDN_AUTO_ADJUST) 0
set ::env(FP_PDN_VWIDTH) 0.3
set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_CORE_RING_VSPACING) 0.4
+set ::env(FP_PDN_CORE_RING_HSPACING) 0.4
+set ::env(FP_PDN_VOFFSET) 10
+set ::env(FP_PDN_HOFFSET) 1
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_VPITCH) 80
+set ::env(FP_PDN_HPITCH) 10.8
set ::env(GLB_RT_MAXLAYER) 4
# set ::env(FP_PDN_CORE_RING) 1
@@ -37,7 +46,7 @@
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 200 30"
+set ::env(DIE_AREA) "0 0 150 20"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -48,7 +57,7 @@
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(BOTTOM_MARGIN_MULT) 1
-set ::env(TOP_MARGIN_MULT) 1
+set ::env(TOP_MARGIN_MULT) 0
set ::env(LEFT_MARGIN_MULT) 10
set ::env(RIGHT_MARGIN_MULT) 0
diff --git a/openlane/mprj2_logic_high/config.tcl b/openlane/mprj2_logic_high/config.tcl
new file mode 100644
index 0000000..452c3c7
--- /dev/null
+++ b/openlane/mprj2_logic_high/config.tcl
@@ -0,0 +1,59 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# This is an analog design. It will be designed by hand.
+# This is a placeholder to get things going.
+set script_dir [file dirname [file normalize [info script]]]
+# User config
+set ::env(DESIGN_NAME) mprj2_logic_high
+
+# Change if needed
+set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/mprj2_logic_high.v
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+# Fill this
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(CELL_PAD) 0
+
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(VDD_NETS) "vccd2"
+set ::env(GND_NETS) "vssd2"
+
+set ::env(FP_PDN_LOWER_LAYER) met2
+set ::env(FP_PDN_UPPER_LAYER) met3
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_CORE_RING_VSPACING) 0.4
+set ::env(FP_PDN_CORE_RING_HSPACING) 0.4
+set ::env(FP_PDN_VOFFSET) 10
+set ::env(FP_PDN_HOFFSET) 1
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_VPITCH) 80
+set ::env(FP_PDN_HPITCH) 10.8
+
+set ::env(GLB_RT_MAXLAYER) 4
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 120 15"
+set ::env(BOTTOM_MARGIN_MULT) 1
+set ::env(TOP_MARGIN_MULT) 1
+set ::env(LEFT_MARGIN_MULT) 0
+set ::env(RIGHT_MARGIN_MULT) 0
diff --git a/openlane/mprj2_logic_high/pin_order.cfg b/openlane/mprj2_logic_high/pin_order.cfg
new file mode 100644
index 0000000..ed44b17
--- /dev/null
+++ b/openlane/mprj2_logic_high/pin_order.cfg
@@ -0,0 +1,2 @@
+#W
+.*
diff --git a/openlane/mprj_logic_high/config.tcl b/openlane/mprj_logic_high/config.tcl
new file mode 100644
index 0000000..0643b68
--- /dev/null
+++ b/openlane/mprj_logic_high/config.tcl
@@ -0,0 +1,58 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set script_dir [file dirname [file normalize [info script]]]
+# User config
+set ::env(DESIGN_NAME) mprj_logic_high
+
+# Change if needed
+set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/mprj_logic_high.v
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# set ::env(FP_CONTEXT_DEF) $script_dir/../mgmt_protect/runs/mgmt_protect/tmp/floorplan/ioPlacer.def.macro_placement.def
+# set ::env(FP_CONTEXT_LEF) $script_dir/../mgmt_protect/runs/mgmt_protect/tmp/merged_unpadded.lef
+
+# Fill this
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(CELL_PAD) 0
+
+set ::env(VDD_NETS) "vccd1"
+set ::env(GND_NETS) "vssd1"
+
+set ::env(FP_PDN_LOWER_LAYER) met2
+set ::env(FP_PDN_UPPER_LAYER) met3
+set ::env(FP_PDN_AUTO_ADJUST) 0
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_CORE_RING_VSPACING) 0.4
+set ::env(FP_PDN_CORE_RING_HSPACING) 0.4
+set ::env(FP_PDN_VOFFSET) 10
+set ::env(FP_PDN_HOFFSET) 1
+set ::env(FP_PDN_VWIDTH) 0.3
+set ::env(FP_PDN_HWIDTH) 0.3
+set ::env(FP_PDN_VPITCH) 80
+set ::env(FP_PDN_HPITCH) 10.8
+
+set ::env(GLB_RT_MAXLAYER) 4
+
+set ::env(PL_RANDOM_INITIAL_PLACEMENT) 1
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 300 23"
+set ::env(PL_TARGET_DENSITY) 0.9
+set ::env(BOTTOM_MARGIN_MULT) 2
+set ::env(TOP_MARGIN_MULT) 2
+set ::env(LEFT_MARGIN_MULT) 15
+set ::env(RIGHT_MARGIN_MULT) 15
