| OpenROAD 0.9.0 e582f2522b |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| Notice 0: Reading LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 437 library cells |
| Notice 0: Finished LEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged_unpadded.lef |
| Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found. |
| Notice 0: |
| Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def |
| Notice 0: Design: user_proj_example |
| Notice 0: Created 612 pins. |
| Notice 0: Created 1518 components and 6703 component-terminals. |
| Notice 0: Created 1015 nets and 1888 connections. |
| Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def |
| Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable |
| [INFO]: Configuring cts characterization... |
| [INFO]: Performing clock tree synthesis... |
| [INFO]: Looking for the following net(s): counter.clk |
| ***************** |
| * TritonCTS 2.0 * |
| ***************** |
| ***************************** |
| * Create characterization * |
| ***************************** |
| Number of created patterns = 50000. |
| Number of created patterns = 100000. |
| Number of created patterns = 150000. |
| Number of created patterns = 200000. |
| Number of created patterns = 250000. |
| Number of created patterns = 300000. |
| Number of created patterns = 313632. |
| Compiling LUT |
| Min. len Max. len Min. cap Max. cap Min. slew Max. slew |
| 2 8 1 39 1 199 |
| [WARNING] 6336 wires are pure wire and no slew degration. |
| TritonCTS forced slew degradation on these wires. |
| Num wire segments: 216048 |
| Num keys in characterization LUT: 1887 |
| Actual min input cap: 2 |
| ********************** |
| * Find clock roots * |
| ********************** |
| Running TritonCTS with user-specified clock roots: counter.clk |
| ************************ |
| * Populate TritonCTS * |
| ************************ |
| Initializing clock nets |
| Looking for clock nets in the design |
| Net "counter.clk" found |
| Initializing clock net for : "counter.clk" |
| Clock net "counter.clk" has 97 sinks |
| TritonCTS found 1 clock nets. |
| **************************** |
| * Check characterization * |
| **************************** |
| The chacterization used 4 buffer(s) types. All of them are in the loaded DB. |
| *********************** |
| * Build clock trees * |
| *********************** |
| Generating H-Tree topology for net counter.clk... |
| Tot. number of sinks: 97 |
| Number of static layers: 0 |
| Wire segment unit: 13000 dbu (13 um) |
| Original sink region: [(36605, 25780), (188865, 224460)] |
| Normalized sink region: [(2.81577, 1.98308), (14.5281, 17.2662)] |
| Width: 11.7123 |
| Height: 15.2831 |
| Level 1 |
| Direction: Vertical |
| # sinks per sub-region: 49 |
| Sub-region size: 11.7123 X 7.64154 |
| Segment length (rounded): 4 |
| Key: 328 outSlew: 11 load: 1 length: 4 isBuffered: 1 |
| Level 2 |
| Direction: Horizontal |
| # sinks per sub-region: 25 |
| Sub-region size: 5.85615 X 7.64154 |
| Segment length (rounded): 2 |
| Key: 53 outSlew: 11 load: 1 length: 2 isBuffered: 1 |
| [WARNING] Creating fake entries in the LUT. |
| Level 3 |
| Direction: Vertical |
| # sinks per sub-region: 13 |
| Sub-region size: 5.85615 X 3.82077 |
| Segment length (rounded): 1 |
| Key: 216289 outSlew: 11 load: 1 length: 1 isBuffered: 1 |
| Stop criterion found. Max number of sinks is (15) |
| Building clock sub nets... |
| Number of sinks covered: 97 |
| Clock topology of net "counter.clk" done. |
| **************** |
| * Post CTS opt * |
| **************** |
| Avg. source sink dist: 35727.2 dbu. |
| Num outlier sinks: 0 |
| ******************** |
| * Write data to DB * |
| ******************** |
| Writing clock net "counter.clk" to DB |
| Created 15 clock buffers. |
| Minimum number of buffers in the clock path: 4. |
| Maximum number of buffers in the clock path: 4. |
| Created 15 clock nets. |
| Fanout distribution for the current clock = 8:2, 10:2, 13:1, 14:1, 16:1, 18:1. |
| Max level of the clock tree: 3. |
| ... End of TritonCTS execution. |
| [INFO]: Legalizing... |
| Warning: could not find power special net |
| Design Stats |
| -------------------------------- |
| total instances 1533 |
| multi row instances 0 |
| fixed instances 846 |
| nets 1030 |
| design area 53897.9 u^2 |
| fixed area 1473.9 u^2 |
| movable area 7409.6 u^2 |
| utilization 14 % |
| utilization padded 14 % |
| rows 83 |
| row height 2.7 u |
| |
| Placement Analysis |
| -------------------------------- |
| total displacement 108.7 u |
| average displacement 0.1 u |
| max displacement 18.7 u |
| original HPWL 49156.0 u |
| legalized HPWL 49158.7 u |
| delta HPWL 0 % |
| |