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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / bfc04b977ca8421587b642c6f0e70db97497e31b / . / openlane / morphle_ycell / runs / morphle_ycell / logs / synthesis / yosys.log
blob: 24ce11d0f316f4001b4a2926e54fc55bc4445b61 [file] [log] [blame]
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
1. Executing Verilog-2005 frontend: /project/openlane/morphle_ycell/../../verilog/morphle/ycell.v
Parsing SystemVerilog input from `/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v' to AST representation.
Generating RTLIL representation for module `\ycfsm'.
Generating RTLIL representation for module `\ycconfig'.
Generating RTLIL representation for module `\ycell'.
Successfully finished Verilog frontend.
2. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/morphle_ycell/runs/morphle_ycell/tmp/synthesis/hierarchy.dot'.
Dumping module ycell to page 1.
3. Executing HIERARCHY pass (managing design hierarchy).
3.1. Analyzing design hierarchy..
Top module: \ycell
Used module: \ycfsm
Used module: \ycconfig
3.2. Analyzing design hierarchy..
Top module: \ycell
Used module: \ycfsm
Used module: \ycconfig
Removed 0 unused modules.
4. Executing SYNTH pass.
4.1. Executing HIERARCHY pass (managing design hierarchy).
4.1.1. Analyzing design hierarchy..
Top module: \ycell
Used module: \ycfsm
Used module: \ycconfig
4.1.2. Analyzing design hierarchy..
Top module: \ycell
Used module: \ycfsm
Used module: \ycconfig
Removed 0 unused modules.
4.2. Executing PROC pass (convert processes to netlists).
4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:92$31 in module ycconfig.
Removed a total of 0 dead cases.
4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 2 assignments to connections.
4.2.4. Executing PROC_INIT pass (extract init attributes).
4.2.5. Executing PROC_ARST pass (detect async resets in processes).
4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:92$31'.
1/1: $1\r[8:0]
Creating decoders for process `\ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:89$30'.
4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\ycconfig.\r' from process `\ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:92$31'.
4.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ycconfig.\cnfg' using process `\ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:89$30'.
created $dff cell `$procdff$61' with positive edge clock.
4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:92$31'.
Removing empty process `ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:92$31'.
Removing empty process `ycconfig.$proc$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:89$30'.
Cleaned up 1 empty switch.
4.3. Executing FLATTEN pass (flatten design).
Deleting now unused module ycconfig.
Deleting now unused module ycfsm.
<suppressed ~3 debug messages>
4.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
Removed 0 unused cells and 44 unused wires.
<suppressed ~1 debug messages>
4.6. Executing CHECK pass (checking for obvious problems).
checking module ycell..
Warning: found logic loop in module ycell:
cell $and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:178$36 ($and)
cell $and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:186$44 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27 ($and)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$21 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$29 ($or)
cell $flatten\hfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27 ($and)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$21 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$29 ($or)
cell $flatten\vfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:180$38 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:183$43 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:188$46 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:191$51 ($mux)
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27_Y
wire $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27_Y
wire $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
wire \bhout [0]
wire \bvout [0]
wire \hback [0]
wire \hfsm.clear
wire \hfsm.lin [0]
wire \hfsm.lmatch [0]
wire \hfsm.lmatchval
wire \hfsm.lmempty
wire \hfsm.match [0]
wire \hfsm.nlmatch [0]
wire \hout [0]
wire \vback [0]
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.lmatch [0]
wire \vfsm.lmatchval
wire \vfsm.lmempty
wire \vfsm.match [0]
wire \vfsm.nlmatch [0]
wire \vout [0]
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\hfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:44$1 ($reduce_or)
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire \hfsm.clear
wire \hfsm.lin [0]
wire \hfsm.linval
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\hfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:44$1 ($reduce_or)
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire \hfsm.clear
wire \hfsm.lin [1]
wire \hfsm.linval
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$21 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20 ($or)
cell $flatten\hfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
wire \hfsm.clear
wire \hfsm.lmatch [0]
wire \hfsm.lmatchval
wire \hfsm.lmempty
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15 ($and)
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$23 ($and)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$25 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24 ($or)
cell $flatten\hfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$23_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24_Y
wire \hfsm.lmatch [0]
wire \hfsm.lmatchval
wire \hfsm.nlmatch [0]
wire \hfsm.nlmempty
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15 ($and)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$21 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$25 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24 ($or)
cell $flatten\hfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
wire $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
wire $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24_Y
wire \hfsm.lmatch [0]
wire \hfsm.lmatchval
wire \hfsm.lmempty
wire \hfsm.nlmatch [0]
wire \hfsm.nlmempty
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$12 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11 ($or)
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [0]
wire \hfsm.lin [0]
wire \hfsm.nlin [0]
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire \hfsm.lmatch [0]
wire \hfsm.nlmatch [0]
Warning: found logic loop in module ycell:
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\hfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire \hfsm.lmatch [1]
wire \hfsm.nlmatch [0]
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\vfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:44$1 ($reduce_or)
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.linval
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\vfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:44$1 ($reduce_or)
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire \vfsm.clear
wire \vfsm.lin [1]
wire \vfsm.linval
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7 ($and)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$21 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$8 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20 ($or)
cell $flatten\vfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$5_Y
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:49$7_Y
wire $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
wire \vfsm.clear
wire \vfsm.lmatch [0]
wire \vfsm.lmatchval
wire \vfsm.lmempty
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15 ($and)
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$23 ($and)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$25 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24 ($or)
cell $flatten\vfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$23_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24_Y
wire \vfsm.lmatch [0]
wire \vfsm.lmatchval
wire \vfsm.nlmatch [0]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15 ($and)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$21 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$25 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24 ($or)
cell $flatten\vfsm.$reduce_or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:46$3 ($reduce_or)
wire $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
wire $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$19_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$18_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:61$24_Y
wire \vfsm.lmatch [0]
wire \vfsm.lmatchval
wire \vfsm.lmempty
wire \vfsm.nlmatch [0]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$10 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$12 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11 ($or)
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [0]
wire \vfsm.lin [0]
wire \vfsm.nlin [0]
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire \vfsm.lmatch [0]
wire \vfsm.nlmatch [0]
Warning: found logic loop in module ycell:
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$14 ($not)
cell $flatten\vfsm.$not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$17 ($not)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13 ($or)
cell $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16 ($or)
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
wire $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
wire \vfsm.lmatch [1]
wire \vfsm.nlmatch [0]
Warning: found logic loop in module ycell:
cell $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$40 ($not)
cell $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$39 ($or)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:180$38 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$41 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:183$43 ($mux)
wire $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$40_Y
wire $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$39_Y
wire \bhout [0]
wire \hback [0]
wire \hfsm.in [0]
Warning: found logic loop in module ycell:
cell $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$40 ($not)
cell $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$39 ($or)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:180$38 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$41 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:183$43 ($mux)
wire $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$40_Y
wire $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:182$39_Y
wire \bhout [0]
wire \hback [1]
wire \hfsm.in [0]
Warning: found logic loop in module ycell:
cell $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$48 ($not)
cell $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$47 ($or)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:188$46 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$49 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:191$51 ($mux)
wire $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$48_Y
wire $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$47_Y
wire \bvout [0]
wire \vback [0]
wire \vfsm.in [0]
Warning: found logic loop in module ycell:
cell $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$48 ($not)
cell $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$47 ($or)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:188$46 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$49 ($mux)
cell $ternary$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:191$51 ($mux)
wire $not$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$48_Y
wire $or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:190$47_Y
wire \bvout [0]
wire \vback [1]
wire \vfsm.in [0]
found and reported 21 problems.
4.7. Executing OPT pass (performing simple optimizations).
4.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ycell..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~7 debug messages>
4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ycell.
Performed a total of 0 changes.
4.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.7.6. Executing OPT_DFF pass (perform DFF optimizations).
4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.7.9. Finished OPT passes. (There is nothing left to do.)
4.8. Executing FSM pass (extract and optimize FSM).
4.8.1. Executing FSM_DETECT pass (finding FSMs in design).
4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.9. Executing OPT pass (performing simple optimizations).
4.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ycell..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~7 debug messages>
4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ycell.
Performed a total of 0 changes.
4.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.9.6. Executing OPT_DFF pass (perform DFF optimizations).
4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.9.9. Finished OPT passes. (There is nothing left to do.)
4.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 2 bits (of 3) from port B of cell ycell.$flatten\cfg.$procmux$60_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell ycell.$flatten\cfg.$procmux$59_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell ycell.$flatten\cfg.$procmux$58_CMP0 ($eq).
4.11. Executing PEEPOPT pass (run peephole optimizers).
4.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module ycell:
created 0 $alu and 0 $macc cells.
4.14. Executing SHARE pass (SAT-based resource sharing).
4.15. Executing OPT pass (performing simple optimizations).
4.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ycell..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~7 debug messages>
4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ycell.
Performed a total of 0 changes.
4.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.15.6. Executing OPT_DFF pass (perform DFF optimizations).
4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.15.9. Finished OPT passes. (There is nothing left to do.)
4.16. Executing MEMORY pass.
4.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
4.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
4.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.18. Executing OPT pass (performing simple optimizations).
4.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.18.3. Executing OPT_DFF pass (perform DFF optimizations).
4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.18.5. Finished fast OPT passes.
4.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
4.20. Executing OPT pass (performing simple optimizations).
4.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ycell..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~7 debug messages>
4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ycell.
Performed a total of 0 changes.
4.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
4.20.6. Executing OPT_SHARE pass.
4.20.7. Executing OPT_DFF pass (perform DFF optimizations).
4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
4.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
4.20.10. Finished OPT passes. (There is nothing left to do.)
4.21. Executing TECHMAP pass (map to technology primitives).
4.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
4.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $eq.
Using template $paramod\_90_pmux\WIDTH=9\S_WIDTH=7 for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_or.
No more expansions possible.
<suppressed ~185 debug messages>
4.22. Executing OPT pass (performing simple optimizations).
4.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
<suppressed ~126 debug messages>
4.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
<suppressed ~48 debug messages>
Removed a total of 16 cells.
4.22.3. Executing OPT_DFF pass (perform DFF optimizations).
4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
Removed 0 unused cells and 93 unused wires.
<suppressed ~1 debug messages>
4.22.5. Finished fast OPT passes.
4.23. Executing ABC pass (technology mapping using ABC).
4.23.1. Extracting gate netlist of module `\ycell' to `<abc-temp-dir>/input.blif'..
Breaking loop using new signal $abcloop$542: \hfsm.clear -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
\hfsm.clear -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [1]
\hfsm.clear -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
\hfsm.clear -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [1]
Breaking loop using new signal $abcloop$543: \hfsm.lmatch [1] -> \hfsm.lmatchval
\hfsm.lmatch [1] -> \hout [1]
\hfsm.lmatch [1] -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [1]
\hfsm.lmatch [1] -> $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27_Y
Breaking loop using new signal $abcloop$544: \vfsm.clear -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [0]
\vfsm.clear -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:56$13_Y [1]
\vfsm.clear -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [0]
\vfsm.clear -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:53$9_Y [1]
Breaking loop using new signal $abcloop$545: \vfsm.lmatch [1] -> \vfsm.lmatchval
\vfsm.lmatch [1] -> \vout [1]
\vfsm.lmatch [1] -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [1]
\vfsm.lmatch [1] -> $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27_Y
Breaking loop using new signal $abcloop$546: \hfsm.in [1] -> \hfsm.inval
\hfsm.in [1] -> \bhout [1]
\hfsm.in [1] -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [1]
Breaking loop using new signal $abcloop$547: \hfsm.lin [0] -> \hfsm.linval
\hfsm.lin [0] -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [0]
\hfsm.lin [0] -> $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27_Y
Breaking loop using new signal $abcloop$548: \hfsm.lin [1] -> \hfsm.linval
\hfsm.lin [1] -> \hout [1]
\hfsm.lin [1] -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [1]
Breaking loop using new signal $abcloop$549: \hfsm.lmatch [0] -> \hfsm.lmatchval
\hfsm.lmatch [0] -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
\hfsm.lmatch [0] -> $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$28_Y
Breaking loop using new signal $abcloop$550: \hfsm.nlmempty -> $flatten\hfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
\hfsm.nlmempty -> $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
\hfsm.nlmempty -> $flatten\hfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [1]
Breaking loop using new signal $abcloop$551: \vfsm.in [1] -> \vfsm.inval
\vfsm.in [1] -> \bvout [1]
\vfsm.in [1] -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [1]
Breaking loop using new signal $abcloop$552: \vfsm.lin [0] -> \vfsm.linval
\vfsm.lin [0] -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [0]
\vfsm.lin [0] -> $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$27_Y
Breaking loop using new signal $abcloop$553: \vfsm.lin [1] -> \vfsm.linval
\vfsm.lin [1] -> \vout [1]
\vfsm.lin [1] -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:54$11_Y [1]
Breaking loop using new signal $abcloop$554: \vfsm.lmatch [0] -> \vfsm.lmatchval
\vfsm.lmatch [0] -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$16_Y [0]
\vfsm.lmatch [0] -> $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:65$28_Y
Breaking loop using new signal $abcloop$555: \vfsm.nlmempty -> $flatten\vfsm.$or$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:60$20_Y
\vfsm.nlmempty -> $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [0]
\vfsm.nlmempty -> $flatten\vfsm.$and$/project/openlane/morphle_ycell/../../verilog/morphle/ycell.v:57$15_Y [1]
Extracted 146 gates and 178 wires to a netlist network with 30 inputs and 24 outputs.
4.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_library <abc-temp-dir>/stdcells.genlib
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash
ABC: + dretime
ABC: + map
ABC: + write_blif <abc-temp-dir>/output.blif
4.23.1.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 7
ABC RESULTS: ANDNOT cells: 37
ABC RESULTS: MUX cells: 12
ABC RESULTS: NAND cells: 1
ABC RESULTS: NOR cells: 17
ABC RESULTS: NOT cells: 7
ABC RESULTS: OR cells: 21
ABC RESULTS: ORNOT cells: 4
ABC RESULTS: internal signals: 124
ABC RESULTS: input signals: 30
ABC RESULTS: output signals: 24
Removing temp directory.
4.24. Executing OPT pass (performing simple optimizations).
4.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
<suppressed ~1 debug messages>
4.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
4.24.3. Executing OPT_DFF pass (perform DFF optimizations).
4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
Removed 0 unused cells and 178 unused wires.
<suppressed ~46 debug messages>
4.24.5. Finished fast OPT passes.
4.25. Executing HIERARCHY pass (managing design hierarchy).
4.25.1. Analyzing design hierarchy..
Top module: \ycell
4.25.2. Analyzing design hierarchy..
Top module: \ycell
Removed 0 unused modules.
4.26. Printing statistics.
=== ycell ===
Number of wires: 124
Number of wire bits: 148
Number of public wires: 44
Number of public wire bits: 68
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 107
$_ANDNOT_ 37
$_AND_ 7
$_DFF_P_ 3
$_MUX_ 12
$_NAND_ 1
$_NOR_ 17
$_NOT_ 7
$_ORNOT_ 3
$_OR_ 20
4.27. Executing CHECK pass (checking for obvious problems).
checking module ycell..
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$556 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$604 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$613 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$652 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$654 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$655 ($_OR_)
wire $abc$541$new_n105_
wire $abc$541$new_n153_
wire $abc$541$new_n155_
wire $abc$541$new_n55_
wire \hfsm.clear
wire \hfsm.lin [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$572 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$575 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$578 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$579 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$585 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$586 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$587 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$588 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$595 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$600 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$601 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$602 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$603 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$606 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$608 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$609 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$610 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$611 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$614 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$615 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$628 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$629 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$630 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$631 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$638 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$640 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n101_
wire $abc$541$new_n104_
wire $abc$541$new_n107_
wire $abc$541$new_n111_
wire $abc$541$new_n115_
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n129_
wire $abc$541$new_n130_
wire $abc$541$new_n131_
wire $abc$541$new_n139_
wire $abc$541$new_n141_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n56_
wire $abc$541$new_n72_
wire $abc$541$new_n75_
wire $abc$541$new_n86_
wire $abc$541$new_n87_
wire $abc$541$new_n88_
wire $abc$541$new_n96_
wire $abc$541$new_n97_
wire \dout [0]
wire \hfsm.in [1]
wire \hfsm.lin [1]
wire \hfsm.lmatch [0]
wire \hfsm.lmatch [1]
wire \hfsm.nlmempty
wire \lout [0]
wire \lout [1]
wire \rout [0]
wire \rout [1]
wire \uout [0]
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.lmatch [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$572 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$575 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$578 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$579 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$585 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$586 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$587 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$588 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$595 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$600 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$601 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$602 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$628 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$629 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$630 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$631 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$638 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$640 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n101_
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n129_
wire $abc$541$new_n130_
wire $abc$541$new_n131_
wire $abc$541$new_n139_
wire $abc$541$new_n141_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n56_
wire $abc$541$new_n72_
wire $abc$541$new_n75_
wire $abc$541$new_n86_
wire $abc$541$new_n87_
wire $abc$541$new_n88_
wire $abc$541$new_n96_
wire $abc$541$new_n97_
wire \dout [0]
wire \hfsm.lmatch [0]
wire \hfsm.lmatch [1]
wire \hfsm.nlmempty
wire \lout [1]
wire \rout [1]
wire \uout [0]
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.lmatch [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$572 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$575 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$578 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$579 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$585 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$586 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$587 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$588 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$595 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$601 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$602 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$603 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$606 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$608 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$609 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$610 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$611 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$628 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$629 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$630 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$631 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$638 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$640 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n104_
wire $abc$541$new_n107_
wire $abc$541$new_n111_
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n129_
wire $abc$541$new_n130_
wire $abc$541$new_n131_
wire $abc$541$new_n139_
wire $abc$541$new_n141_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n56_
wire $abc$541$new_n72_
wire $abc$541$new_n75_
wire $abc$541$new_n86_
wire $abc$541$new_n87_
wire $abc$541$new_n88_
wire $abc$541$new_n96_
wire $abc$541$new_n97_
wire \dout [0]
wire \hfsm.in [1]
wire \hfsm.lmatch [0]
wire \hfsm.lmatch [1]
wire \hfsm.nlmempty
wire \lout [0]
wire \lout [1]
wire \rout [0]
wire \rout [1]
wire \uout [0]
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.lmatch [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$572 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$575 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$578 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$579 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$585 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$586 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$587 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$588 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$595 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$603 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$606 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$608 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$609 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$619 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$620 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$621 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$622 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$638 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$640 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n104_
wire $abc$541$new_n107_
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n120_
wire $abc$541$new_n121_
wire $abc$541$new_n122_
wire $abc$541$new_n139_
wire $abc$541$new_n141_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n56_
wire $abc$541$new_n72_
wire $abc$541$new_n75_
wire $abc$541$new_n86_
wire $abc$541$new_n87_
wire $abc$541$new_n88_
wire $abc$541$new_n96_
wire $abc$541$new_n97_
wire \dout [0]
wire \hfsm.lmatch [0]
wire \hfsm.lmatch [1]
wire \hfsm.nlmempty
wire \lout [0]
wire \rout [0]
wire \uout [0]
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.lmatch [0]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$586 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$587 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$588 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$638 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$640 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
wire $abc$541$new_n139_
wire $abc$541$new_n141_
wire $abc$541$new_n56_
wire $abc$541$new_n87_
wire $abc$541$new_n88_
wire \hfsm.lmatch [0]
wire \hfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$595 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$603 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$604 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$606 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$608 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$609 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$610 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$611 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$614 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$615 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$641 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$642 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
wire $abc$541$new_n104_
wire $abc$541$new_n105_
wire $abc$541$new_n107_
wire $abc$541$new_n111_
wire $abc$541$new_n115_
wire $abc$541$new_n142_
wire $abc$541$new_n143_
wire $abc$541$new_n56_
wire $abc$541$new_n96_
wire $abc$541$new_n97_
wire \hfsm.in [1]
wire \hfsm.lin [1]
wire \hfsm.lmatch [1]
wire \hfsm.nlmempty
wire \lout [0]
wire \rout [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$595 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$638 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$640 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
wire $abc$541$new_n139_
wire $abc$541$new_n141_
wire $abc$541$new_n56_
wire $abc$541$new_n96_
wire $abc$541$new_n97_
wire \hfsm.lmatch [1]
wire \hfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$557 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$642 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$643 ($_ANDNOT_)
wire $abc$541$new_n143_
wire $abc$541$new_n56_
wire \hfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$572 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$573 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$575 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$578 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$579 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$632 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$633 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$636 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$637 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$647 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$648 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n133_
wire $abc$541$new_n137_
wire $abc$541$new_n148_
wire $abc$541$new_n149_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n72_
wire $abc$541$new_n73_
wire $abc$541$new_n75_
wire \dout [0]
wire \uout [0]
wire \vfsm.clear
wire \vfsm.in [1]
wire \vfsm.lin [0]
wire \vfsm.lin [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$573 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$647 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$648 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n148_
wire $abc$541$new_n149_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n73_
wire \vfsm.clear
wire \vfsm.lin [0]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$573 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$637 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$647 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$648 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n148_
wire $abc$541$new_n149_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire $abc$541$new_n73_
wire \vfsm.clear
wire \vfsm.lin [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$587 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$588 ($_ANDNOT_)
wire $abc$541$new_n88_
wire \hfsm.lmatch [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$589 ($_AND_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$590 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$591 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$632 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$633 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$636 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$637 ($_ANDNOT_)
wire $abc$541$new_n133_
wire $abc$541$new_n137_
wire $abc$541$new_n90_
wire \dout [1]
wire \uout [1]
wire \vfsm.in [1]
wire \vfsm.lin [1]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$590 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$591 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$632 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$633 ($_MUX_)
wire $abc$541$new_n133_
wire \dout [1]
wire \uout [1]
wire \vfsm.in [1]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$596 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$597 ($_ANDNOT_)
wire $abc$541$new_n97_
wire \hfsm.lmatch [1]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$604 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$605 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$606 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$608 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$609 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$610 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$611 ($_MUX_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$614 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$615 ($_ANDNOT_)
wire $abc$541$new_n105_
wire $abc$541$new_n106_
wire $abc$541$new_n107_
wire $abc$541$new_n111_
wire $abc$541$new_n115_
wire \hfsm.in [1]
wire \hfsm.lin [1]
wire \lout [0]
wire \rout [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$612 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$613 ($_ANDNOT_)
wire $abc$541$new_n113_
wire \hfsm.lin [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$614 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$615 ($_ANDNOT_)
wire $abc$541$new_n115_
wire \hfsm.lin [1]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$622 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire \vfsm.clear
wire \vfsm.lmatch [0]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$616 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$631 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$658 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$660 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$661 ($_OR_)
wire $abc$541$new_n117_
wire $abc$541$new_n118_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire $abc$541$new_n159_
wire $abc$541$new_n161_
wire \vfsm.clear
wire \vfsm.lmatch [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$620 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$621 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$622 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
wire $abc$541$new_n118_
wire $abc$541$new_n121_
wire $abc$541$new_n122_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire \vfsm.lmatch [0]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$629 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$630 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$631 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$644 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$646 ($_OR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
wire $abc$541$new_n118_
wire $abc$541$new_n130_
wire $abc$541$new_n131_
wire $abc$541$new_n145_
wire $abc$541$new_n147_
wire \vfsm.lmatch [1]
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$617 ($_NOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$648 ($_ANDNOT_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$649 ($_ANDNOT_)
wire $abc$541$new_n118_
wire $abc$541$new_n149_
wire \vfsm.nlmempty
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$621 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$622 ($_ANDNOT_)
wire $abc$541$new_n122_
wire \vfsm.lmatch [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$630 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$631 ($_ANDNOT_)
wire $abc$541$new_n131_
wire \vfsm.lmatch [1]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$634 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$635 ($_ANDNOT_)
wire $abc$541$new_n135_
wire \vfsm.lin [0]
Warning: found logic loop in module ycell:
cell $abc$541$auto$blifparse.cc:377:parse_blif$636 ($_NOR_)
cell $abc$541$auto$blifparse.cc:377:parse_blif$637 ($_ANDNOT_)
wire $abc$541$new_n137_
wire \vfsm.lin [1]
found and reported 28 problems.
5. Executing SHARE pass (SAT-based resource sharing).
6. Executing OPT pass (performing simple optimizations).
6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ycell..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ycell.
Performed a total of 0 changes.
6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ycell'.
Removed a total of 0 cells.
6.6. Executing OPT_DFF pass (perform DFF optimizations).
6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ycell.
6.9. Finished OPT passes. (There is nothing left to do.)
7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
Removed 0 unused cells and 11 unused wires.
<suppressed ~11 debug messages>
8. Printing statistics.
=== ycell ===
Number of wires: 113
Number of wire bits: 129
Number of public wires: 33
Number of public wire bits: 49
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 107
$_ANDNOT_ 37
$_AND_ 7
$_DFF_P_ 3
$_MUX_ 12
$_NAND_ 1
$_NOR_ 17
$_NOT_ 7
$_ORNOT_ 3
$_OR_ 20
9. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_4 (noninv, pins=3, area=23.77) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtp_4 (noninv, pins=4, area=28.78) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_4 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_4 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_4 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_4 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
\sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
9.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\ycell':
mapped 3 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_4 cells.
10. Printing statistics.
=== ycell ===
Number of wires: 113
Number of wire bits: 129
Number of public wires: 33
Number of public wire bits: 49
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 107
$_ANDNOT_ 37
$_AND_ 7
$_MUX_ 12
$_NAND_ 1
$_NOR_ 17
$_NOT_ 7
$_ORNOT_ 3
$_OR_ 20
sky130_fd_sc_hd__dfxtp_4 3
11. Executing ABC pass (technology mapping using ABC).
11.1. Extracting gate netlist of module `\ycell' to `/tmp/yosys-abc-lSCGP5/input.blif'..
Breaking loop using new signal $abcloop$663: \hfsm.lmatch [1] -> $abc$541$new_n97_
\hfsm.lmatch [1] -> $abc$541$new_n101_
\hfsm.lmatch [1] -> $abc$541$new_n104_
\hfsm.lmatch [1] -> $abc$541$new_n139_
Breaking loop using new signal $abcloop$664: \vfsm.lmatch [1] -> $abc$541$new_n72_
\vfsm.lmatch [1] -> $abc$541$new_n90_
\vfsm.lmatch [1] -> $abc$541$new_n131_
\vfsm.lmatch [1] -> $abc$541$new_n145_
Breaking loop using new signal $abcloop$665: \hfsm.in [1] -> \rout [1]
\hfsm.in [1] -> $abc$541$new_n115_
\hfsm.in [1] -> $abc$541$new_n154_
Breaking loop using new signal $abcloop$666: \hfsm.lin [1] -> $abc$541$new_n101_
\hfsm.lin [1] -> $abc$541$new_n105_
\hfsm.lin [1] -> $abc$541$new_n115_
Breaking loop using new signal $abcloop$667: \hfsm.lin [0] -> $abc$541$new_n104_
\hfsm.lin [0] -> $abc$541$new_n105_
\hfsm.lin [0] -> $abc$541$new_n113_
Breaking loop using new signal $abcloop$668: \hfsm.lmatch [0] -> $abc$541$new_n88_
\hfsm.lmatch [0] -> $abc$541$new_n106_
\hfsm.lmatch [0] -> $abc$541$new_n139_
Breaking loop using new signal $abcloop$669: \vfsm.in [1] -> \dout [1]
\vfsm.in [1] -> $abc$541$new_n137_
\vfsm.in [1] -> $abc$541$new_n160_
Breaking loop using new signal $abcloop$670: \vfsm.lin [0] -> $abc$541$new_n72_
\vfsm.lin [0] -> $abc$541$new_n73_
\vfsm.lin [0] -> $abc$541$new_n135_
Breaking loop using new signal $abcloop$671: \vfsm.lin [1] -> $abc$541$new_n73_
\vfsm.lin [1] -> $abc$541$new_n90_
\vfsm.lin [1] -> $abc$541$new_n137_
Breaking loop using new signal $abcloop$672: \vfsm.lmatch [0] -> $abc$541$new_n74_
\vfsm.lmatch [0] -> $abc$541$new_n122_
\vfsm.lmatch [0] -> $abc$541$new_n145_
Breaking loop using new signal $abcloop$673: \hfsm.clear -> $abc$541$new_n55_
Breaking loop using new signal $abcloop$674: \hfsm.nlmempty -> $abc$541$new_n56_
Breaking loop using new signal $abcloop$675: \vfsm.clear -> $abc$541$new_n117_
Breaking loop using new signal $abcloop$676: \vfsm.nlmempty -> $abc$541$new_n118_
Extracted 104 gates and 134 wires to a netlist network with 30 inputs and 24 outputs.
11.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-lSCGP5/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-lSCGP5/abc.script".
ABC:
ABC: + read_blif /tmp/yosys-abc-lSCGP5/input.blif
ABC: + read_lib -w /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/trimmed.lib
ABC: Parsing finished successfully. Parsing time = 0.03 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/project/openlane/morphle_ycell/runs/morphle_ycell/tmp/trimmed.lib" has 61 cells (8 skipped: 8 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.04 sec
ABC: Memory = 2.51 MB. Time = 0.04 sec
ABC: + read_constr -v /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/synthesis/yosys.sdc
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_8".
ABC: Setting output load to be 17.650000.
ABC: + read_constr /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/synthesis/yosys.sdc
ABC: + fx
ABC: + mfs
ABC: + strash
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + refactor
ABC: + balance
ABC: + rewrite
ABC: + rewrite -z
ABC: + balance
ABC: + refactor -z
ABC: + rewrite -z
ABC: + balance
ABC: + retime -D -D 0 -M 5
ABC: + scleanup
ABC: Error: The network is combinational.
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000
ABC: + retime -D -D 0
ABC: + buffer -N 5 -S 0.0
ABC: + upsize -D 0
ABC: + dnsize -D 0
ABC: + stime -p
ABC: WireLoad = "none" Gates = 103 ( 17.5 %) Cap = 10.4 ff ( 5.9 %) Area = 884.60 ( 86.4 %) Delay = 1891.37 ps ( 35.9 %)
ABC: Path 0 -- 3 : 0 4 pi A = 0.00 Df = 30.2 -19.4 ps S = 48.9 ps Cin = 0.0 ff Cout = 26.2 ff Cmax = 0.0 ff G = 0
ABC: Path 1 -- 59 : 1 5 sky130_fd_sc_hd__inv_8 A = 11.26 Df = 62.0 -7.3 ps S = 37.6 ps Cin = 17.7 ff Cout = 18.4 ff Cmax =1035.5 ff G = 99
ABC: Path 2 -- 60 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 300.5 -137.6 ps S = 52.4 ps Cin = 2.4 ff Cout = 8.5 ff Cmax = 514.5 ff G = 339
ABC: Path 3 -- 72 : 2 1 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 525.4 -261.0 ps S = 46.7 ps Cin = 2.4 ff Cout = 4.9 ff Cmax = 514.5 ff G = 193
ABC: Path 4 -- 73 : 1 3 sky130_fd_sc_hd__buf_6 A = 11.26 Df = 654.2 -281.9 ps S = 61.3 ps Cin = 4.6 ff Cout = 24.8 ff Cmax = 785.5 ff G = 511
ABC: Path 5 -- 74 : 1 3 sky130_fd_sc_hd__inv_8 A = 11.26 Df = 695.3 -295.5 ps S = 25.0 ps Cin = 17.7 ff Cout = 8.8 ff Cmax =1035.5 ff G = 46
ABC: Path 6 -- 101 : 2 3 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 828.9 -178.6 ps S = 79.8 ps Cin = 2.4 ff Cout = 21.9 ff Cmax = 514.5 ff G = 905
ABC: Path 7 -- 102 : 2 1 sky130_fd_sc_hd__or2_4 A = 8.76 Df = 944.3 -61.7 ps S = 46.8 ps Cin = 2.4 ff Cout = 4.9 ff Cmax = 514.5 ff G = 193
ABC: Path 8 -- 103 : 1 3 sky130_fd_sc_hd__buf_6 A = 11.26 Df =1056.1 -42.6 ps S = 66.5 ps Cin = 4.6 ff Cout = 27.6 ff Cmax = 785.5 ff G = 571
ABC: Path 9 -- 104 : 1 2 sky130_fd_sc_hd__inv_8 A = 11.26 Df =1085.0 -28.6 ps S = 26.4 ps Cin = 17.7 ff Cout = 9.7 ff Cmax =1035.5 ff G = 52
ABC: Path 10 -- 106 : 4 3 sky130_fd_sc_hd__o22a_4 A = 17.52 Df =1365.7 -110.3 ps S = 125.2 ps Cin = 4.6 ff Cout = 38.6 ff Cmax = 530.1 ff G = 824
ABC: Path 11 -- 107 : 1 1 sky130_fd_sc_hd__inv_8 A = 11.26 Df =1417.1 -136.5 ps S = 26.3 ps Cin = 17.7 ff Cout = 2.5 ff Cmax =1035.5 ff G = 13
ABC: Path 12 -- 108 : 3 2 sky130_fd_sc_hd__or3_4 A = 11.26 Df =1603.7 -81.4 ps S = 70.1 ps Cin = 2.4 ff Cout = 7.3 ff Cmax = 531.9 ff G = 293
ABC: Path 13 -- 153 : 3 1 sky130_fd_sc_hd__and3_4 A = 11.26 Df =1765.4 -69.3 ps S = 58.1 ps Cin = 2.4 ff Cout = 9.3 ff Cmax = 532.8 ff G = 358
ABC: Path 14 -- 154 : 2 1 sky130_fd_sc_hd__nor2_4 A = 11.26 Df =1891.4 -149.5 ps S = 138.4 ps Cin = 8.7 ff Cout = 17.6 ff Cmax = 251.8 ff G = 202
ABC: Start-point = pi2 (\cfg.cnfg [0]). End-point = po22 (\vfsm.nlmempty).
ABC: + print_stats -m
ABC: netlist : i/o = 30/ 24 lat = 0 nd = 103 edge = 221 area =884.81 delay =15.00 lev = 15
ABC: + write_blif /tmp/yosys-abc-lSCGP5/output.blif
11.1.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__a211o_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__a32o_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 7
ABC RESULTS: sky130_fd_sc_hd__and3_2 cells: 3
ABC RESULTS: sky130_fd_sc_hd__and3_4 cells: 1
ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__buf_2 cells: 1
ABC RESULTS: sky130_fd_sc_hd__buf_6 cells: 3
ABC RESULTS: sky130_fd_sc_hd__inv_8 cells: 12
ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 11
ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 1
ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 28
ABC RESULTS: sky130_fd_sc_hd__nor2_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 3
ABC RESULTS: sky130_fd_sc_hd__nor4_2 cells: 2
ABC RESULTS: sky130_fd_sc_hd__o21a_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__o22a_4 cells: 2
ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 10
ABC RESULTS: sky130_fd_sc_hd__or2_4 cells: 4
ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 3
ABC RESULTS: sky130_fd_sc_hd__or3_4 cells: 2
ABC RESULTS: internal signals: 80
ABC RESULTS: input signals: 30
ABC RESULTS: output signals: 24
Removing temp directory.
12. Executing SETUNDEF pass (replace undef values with defined constants).
13. Executing HILOMAP pass (mapping to constant drivers).
14. Executing SPLITNETS pass (splitting up multi-bit signals).
15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ycell..
Removed 0 unused cells and 151 unused wires.
<suppressed ~4 debug messages>
16. Executing INSBUF pass (insert buffer cells for connected wires).
Added ycell.$auto$insbuf.cc:79:execute$780: \confclk -> \confclko
Added ycell.$auto$insbuf.cc:79:execute$781: \hempty -> \hempty2
Added ycell.$auto$insbuf.cc:79:execute$782: \reset -> \reseto
Added ycell.$auto$insbuf.cc:79:execute$783: \vempty -> \vempty2
17. Executing CHECK pass (checking for obvious problems).
checking module ycell..
Warning: Wire ycell.\vempty2 is used but has no driver.
Warning: Wire ycell.\vempty is used but has no driver.
Warning: Wire ycell.\uout [1] is used but has no driver.
Warning: Wire ycell.\uout [0] is used but has no driver.
Warning: Wire ycell.\rout [1] is used but has no driver.
Warning: Wire ycell.\rout [0] is used but has no driver.
Warning: Wire ycell.\reseto is used but has no driver.
Warning: Wire ycell.\lout [1] is used but has no driver.
Warning: Wire ycell.\lout [0] is used but has no driver.
Warning: Wire ycell.\hempty2 is used but has no driver.
Warning: Wire ycell.\hempty is used but has no driver.
Warning: Wire ycell.\dout [1] is used but has no driver.
Warning: Wire ycell.\dout [0] is used but has no driver.
Warning: Wire ycell.\confclko is used but has no driver.
Warning: Wire ycell.\cbitout is used but has no driver.
found and reported 15 problems.
18. Printing statistics.
=== ycell ===
Number of wires: 117
Number of wire bits: 125
Number of public wires: 38
Number of public wire bits: 46
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 110
sky130_fd_sc_hd__a211o_4 2
sky130_fd_sc_hd__a32o_4 2
sky130_fd_sc_hd__and2_2 7
sky130_fd_sc_hd__and3_2 3
sky130_fd_sc_hd__and3_4 1
sky130_fd_sc_hd__buf_1 2
sky130_fd_sc_hd__buf_2 5
sky130_fd_sc_hd__buf_6 3
sky130_fd_sc_hd__dfxtp_4 3
sky130_fd_sc_hd__inv_8 12
sky130_fd_sc_hd__nand2_2 11
sky130_fd_sc_hd__nand3_2 1
sky130_fd_sc_hd__nor2_2 28
sky130_fd_sc_hd__nor2_4 2
sky130_fd_sc_hd__nor3_2 3
sky130_fd_sc_hd__nor4_2 2
sky130_fd_sc_hd__o21a_4 2
sky130_fd_sc_hd__o22a_4 2
sky130_fd_sc_hd__or2_2 10
sky130_fd_sc_hd__or2_4 4
sky130_fd_sc_hd__or3_2 3
sky130_fd_sc_hd__or3_4 2
Chip area for module '\ycell': 975.936000
19. Executing Verilog backend.
Dumping module `\ycell'.
Warnings: 64 unique messages, 64 total
End of script. Logfile hash: 03869296e2, CPU: user 0.80s system 0.02s, MEM: 43.77 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 45% 4x stat (0 sec), 25% 2x abc (0 sec), ...