commit 27200e957abe57219655ca559a260bd43b6e2990
author Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Nov 25 22:07:02 2020 +0200
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Nov 25 22:07:02 2020 +0200
tree 2faf4fd70a5b0b9f90fab48fa81d454aa666fffd
parent 365f5d7971bf26680fc4cf64d52e4de44bd3eb19

Add more missing USE_POWER_PINS

- in user_id_programming and simple_por

verilog/rtl/user_id_programming.v

diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 526a802..934f9d7 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -7,8 +7,10 @@
 module user_id_programming #(
     parameter [ 0:0] USER_PROJECT_ID = 32'h0
 ) (
+`ifdef USE_POWER_PINS
     inout vdd1v8,
     inout vss,
+`endif
     output [31:0] mask_rev
 );
     wire [31:0] mask_rev;