commit 21a9aac19537bf1a1e90e356d67a6b0e05bf1091
author Tim Edwards <tim@opencircuitdesign.com> Mon Oct 12 22:05:18 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Mon Oct 12 22:05:18 2020 -0400
tree 96dea37f5673c8e442119bd5fe9ec8416cd5d51c
parent e2ef673adf739e8eec22d45574b754a0269b14e3

Testbench simulations are now all working correctly with the pre-release
version of sky130_fd_io.

verilog/rtl/user_id_programming.v

diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 30f5eb8..5133605 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -6,6 +6,8 @@
 module user_id_programming #(
     parameter [ 0:0] USER_PROJECT_ID = 32'h0
 ) (
+    inout vdd1v8,
+    inout vss,
     output [31:0] mask_rev
 );
     wire [31:0] mask_rev;
@@ -15,12 +17,10 @@
     // For the mask revision input, use an array of digital constant logic cells
 
     sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
-        `ifdef LVS
             .VPWR(vdd1v8),
             .VPB(vdd1v8),
             .VNB(vss),
             .VGND(vss),
-        `endif
             .HI(user_proj_id_high),
             .LO(user_proj_id_low)
     );