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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / 0f49eb21af59662e6d367f336ea8cd3362b63c27
commit0f49eb21af59662e6d367f336ea8cd3362b63c27[log] [tgz]
authorJecel Assumpcao Jr <jecel@merlintec.com>Thu Nov 26 20:47:42 2020 -0300
committerJecel Assumpcao Jr <jecel@merlintec.com>Thu Nov 26 20:47:42 2020 -0300
tree7f7416a1bbbc2b2a9c91b98785931bba96cee3b2
parent57310a9bd984802ec7702128f53e5f6addd4eb63 [diff]
parent011d750d9806f03d1a5dcfba23f21371f87b9f7d [diff]
Merge https://github.com/efabless/caravel into main
tree: 7f7416a1bbbc2b2a9c91b98785931bba96cee3b2
  1. def/
  2. doc/
  3. gds/
  4. lef/
  5. macros/
  6. mag/
  7. openlane/
  8. scripts/
  9. spi/
  10. verilog/
  11. _config.yml
  12. info.yaml
  13. LICENSE
  14. LICENSE-2.0
  15. Makefile
  16. README.md
  17. README_MORPHLE_LOGIC.md
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC can be found here

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.