- 581068f Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
- 08cd6eb add default nettype none by Matt Venn · 4 years, 4 months ago
- 706c312 Reset iomem_ready to 0 only in one block by Ahmed Ghazy · 4 years, 5 months ago
- f46273f Fix for the synthesis warnings about iomem_rdata by Ahmed Ghazy · 4 years, 5 months ago
- d01c637 Modified the mprj_ctrl.v verilog to be completely clear about how by Tim Edwards · 4 years, 5 months ago
- 22d29d6 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
- 0445c08 Revised the mprj_ctrl module verilog so that it does not generate by Tim Edwards · 4 years, 5 months ago
- ba32890 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
- e6eda80 Fix a typo in a previous fix... by Ahmed Ghazy · 4 years, 5 months ago
- 0b6219d Fix to an issue with index arithmetic by Ahmed Ghazy · 4 years, 5 months ago
- 496a08a Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
- 9eda80d Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
- ca2f318 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 6 months ago
- 89f0924 Made corrections; GPIO testbench now passes. by Tim Edwards · 4 years, 6 months ago
- 251e0df Serial chain loading of the I/O configurations is now working. by Tim Edwards · 4 years, 6 months ago
- 44bab47 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 6 months ago
- c18c474 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 4 years, 6 months ago
- 04ba17f Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 4 years, 6 months ago
- 0d14e6e harness phase1 initial commit by shalan · 4 years, 7 months ago
