update README
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--- a/README.md
+++ b/README.md
@@ -1,71 +1,28 @@
-# CIIC Harness
+# RAPcore Caravel Flow
-A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
+https://rapcores.github.io/rapcores/
-<p align=”center”>
-<img src="/doc/ciic_harness.png" width="75%" height="75%">
-</p>
+The Robotic Application Processing Core on the OpenMPW/Caravel Shuttle run sponsored by Google .
-## Getting Started:
+RAPcore is a project targeting FPGAs and ASIC devices for the next generation of motor and motion
+control applications. It is a peripheral that sits between firmwares and motors to free up
+processing on the microcontroller and greatly simplify the motor driver.
-Start by cloning the repo and uncompressing the files.
-```bash
-git clone https://github.com/efabless/caravel.git
-cd caravel
-make uncompress
-```
+## Features
-Install the required version of the PDK by running the following commands:
+- Onboard stepper motor commutator with microstepping
+- Fixed Point Step-Timing Algorithm
+- High-speed Quadrature Encoder Accumulator
+- High-Speed SPI Bus
-```bash
-export PDK_ROOT=<The place where you want to install the pdk>
-make pdk
-```
+## Build Requirements
-Then, you can learn more about the caravel chip by watching these video:
-- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
-- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
-- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
+See INSTALL.md for local development instructions.
-## Aboard Caravel:
+## Documentation
-Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
+https://rapcores.github.io/rapcores/
-If you will use OpenLANE to harden your design, go through the instructions in this [README.md][0].
+## License
-Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
-
-- Magic installed on your machine. We may provide a Dockerized version later.
-- You have your user_project_wrapper.gds under `./gds/` in the Caravel directory.
-
-Run the following command:
-
-```bash
-export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step>
-make
-```
-
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
-
-## Managment SoC
-The managment SoC runs firmware that can be used to:
-- Configure User Project I/O pads
-- Observe and control User Project signals (through on-chip logic analyzer probes)
-- Control the User Project power supply
-
-The memory map of the management SoC can be found [here](verilog/rtl/README)
-
-## User Project Area
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel_datasheet.pdf) for details.
-The repository contains a [sample user project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>
-
-<p align=”center”>
-<img src="/doc/counter_32.png" width="50%" height="50%">
-</p>
-
-The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the User Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
-2. Configure the User Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
-3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
-
-[0]: openlane/README.md
+[ISC License](https://en.wikipedia.org/wiki/ISC_license).
