commit ec8dd91aa8746a002b1232e8da195b31c9de4042
author Steve Kelly <kd2cca@gmail.com> Sun Dec 20 02:03:46 2020 -0500
committer Steve Kelly <kd2cca@gmail.com> Sun Dec 20 02:03:46 2020 -0500
tree 1a9f6791f1c0321d55459bd5098597d97fdb4148
parent 80249b44988a741903d7dfea0e7181093f8c5c22

cleanup tb for GL

verilog/dv/caravel/rapcore/io_ports/Makefile

diff --git a/verilog/dv/caravel/rapcore/io_ports/Makefile b/verilog/dv/caravel/rapcore/io_ports/Makefile
index f34a4d6..d07edeb 100644
--- a/verilog/dv/caravel/rapcore/io_ports/Makefile
+++ b/verilog/dv/caravel/rapcore/io_ports/Makefile
@@ -34,9 +34,7 @@
 	-o $@ $<
 else
 	iverilog -DPROJ_GL -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
-	-I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src  -I $(RAPCORES_PATH)/testbench \
-	-I $(RAPCORES_PATH)/boards -I $(GL_PATH) \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \
 	-o $@ $<
 endif
 

verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v

diff --git a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
index 57cb042..163af61 100644
--- a/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/rapcore/io_ports/io_ports_tb.v
@@ -4,35 +4,35 @@
 
 `include "defines.v"
 `include "mpw_one_defines.v"
-`include "macro_params.v"
-`include "constants.v"
-`include "quad_enc.v"
-`include "spi.v"
-`include "dda_timer.v"
-`include "spi_state_machine.v"
-`include "microstepper/chargepump.v"
-`include "microstepper/microstepper_control.v"
-`include "microstepper/mytimer_8.v"
-`include "microstepper/mytimer_10.v"
-`include "microstepper/microstep_counter.v"
-`include "microstepper/cosine.v"
-`include "microstepper/analog_out.v"
-`include "microstepper/microstepper_top.v"
-`include "rapcore.v"
-`include "hbridge_coil.v"
-`include "pwm_duty.v"
-`include "rapcore_harness_tb.v"
 
 //`define USE_POWER_PINS
 
 `ifdef PROJ_GL
-  `include "rapcores.lvs.powered.v"
+    `include "../gl/rapcores.v"
 `else
-  `include "rapcores.v"
+    `include "rapcores.v"
+    `include "macro_params.v"
+    `include "constants.v"
+    `include "quad_enc.v"
+    `include "spi.v"
+    `include "dda_timer.v"
+    `include "spi_state_machine.v"
+    `include "microstepper/chargepump.v"
+    `include "microstepper/microstepper_control.v"
+    `include "microstepper/mytimer_8.v"
+    `include "microstepper/mytimer_10.v"
+    `include "microstepper/microstep_counter.v"
+    `include "microstepper/cosine.v"
+    `include "microstepper/analog_out.v"
+    `include "microstepper/microstepper_top.v"
+    `include "rapcore.v"
 `endif
 
+`include "rapcore_harness_tb.v"
 `include "caravel.v"
 `include "spiflash.v"
+`include "hbridge_coil.v"
+`include "pwm_duty.v"
 
 module io_ports_tb;
 	reg clock;