Merge remote-tracking branch 'origin/jr/cv_tb' into sjk/tk_rc61
diff --git a/openlane/rapcores/config.tcl b/openlane/rapcores/config.tcl
index d81e708..338e3ea 100644
--- a/openlane/rapcores/config.tcl
+++ b/openlane/rapcores/config.tcl
@@ -59,6 +59,12 @@
# block met5 with obstruction
set ::env(GLB_RT_OBS) "met5 0 0 1000 1000"
set ::env(GLB_RT_MAXLAYER) 5
+set ::env(VDD_PIN) vccd1
+set ::env(GND_PIN) vssd1
+set ::env(FP_PDN_VOFFSET) "14"
+set ::env(FP_PDN_VPITCH) "180"
+set ::env(FP_PDN_HOFFSET) "14"
+set ::env(FP_PDN_HPITCH) "180"
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
diff --git a/rapcores b/rapcores
index 7afb4a1..2a22260 160000
--- a/rapcores
+++ b/rapcores
@@ -1 +1 @@
-Subproject commit 7afb4a10af865163dffdba6908b7a4f44c4ec243
+Subproject commit 2a22260b4f7fb82b172db9bb8b3b2689d0006b93
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index d6c2bf6..e47c2f6 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -18,11 +18,14 @@
VERILOG_PATH = ../../../..
RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
+BEHAVIOURAL_MODELS = ../../
+RAPCORES_PATH = ../../../../../rapcores
-GCC_PATH?=/ef/apps/bin
+GCC_PATH?=//opt/riscv32/bin
GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+SIM?=RTL
SIM?=RTL
@@ -37,13 +40,14 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench \
+ -o $@ $<
else
iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
+ -o $@ $<
endif
+# MERGE: -I $(VERILOG_PATH) maybe needed for GL
%.vcd: %.vvp
vvp $<
@@ -52,7 +56,7 @@
${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
# to fix flash base address
sed -i 's/@10000000/@00000000/g' $@
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
index a159f0a..28ba9e2 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -49,12 +49,48 @@
reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [63:32] as outputs from the cpu
+ reg_la0_ena = 0xFFFFFFFF; // [31:0]
+ reg_la1_ena = 0x00000000; // [95:64]
+ reg_la2_ena = 0x00000000; // [63:32]
+ reg_la3_ena = 0xFFFFFFFF; // [127:96]
+
+ // Set Counter value to zero through LA probes [63:32]
+ reg_la2_data = 0x00000003;
+
}
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index c680a0b..222e5e3 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -17,6 +17,34 @@
`timescale 1 ns / 1 ps
+`include "defines.v"
+`include "rapcore_caravel_defines.v"
+`include "macro_params.v"
+`include "constants.v"
+`include "quad_enc.v"
+`include "spi.v"
+`include "dda_timer.v"
+`include "spi_state_machine.v"
+`include "microstepper/chargepump.v"
+`include "microstepper/microstepper_control.v"
+`include "microstepper/mytimer_8.v"
+`include "microstepper/mytimer_10.v"
+`include "microstepper/microstep_counter.v"
+`include "microstepper/cosine.v"
+`include "microstepper/analog_out.v"
+`include "microstepper/microstepper_top.v"
+`include "rapcore.v"
+`include "hbridge_coil.v"
+`include "pwm_duty.v"
+
+//`define USE_POWER_PINS
+
+`ifdef PROJ_GL
+ `include "gl/rapcore.v"
+`else
+ `include "rapcore_caravel.v"
+`endif
+
`include "caravel.v"
`include "spiflash.v"
@@ -48,7 +76,7 @@
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
- repeat (1000) @(posedge clock);
+ repeat (4000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
@@ -98,7 +126,7 @@
end
always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ #1 $display("MPRJ-IO state = %b ", mprj_io[37:0]);
end
wire flash_csb;
@@ -112,6 +140,96 @@
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
+
+ reg step;
+ reg dir;
+ reg enable_in;
+ wire [12:0] target_current1;
+ wire [12:0] target_current2;
+ wire signed [12:0] current1;
+ wire signed [12:0] current2;
+
+ wire analog_out1;
+ wire analog_out2;
+ reg analog_cmp1;
+ reg analog_cmp2;
+ reg [40:0] step_clock;
+ reg [20:0] cnt;
+ reg [12:0] current_abs1;
+ reg [12:0] current_abs2;
+ wire phase_a1_l;
+ wire phase_a2_l;
+ wire phase_b1_l;
+ wire phase_b2_l;
+ wire phase_a1_h;
+ wire phase_a2_h;
+ wire phase_b1_h;
+ wire phase_b2_h;
+ wire resetn;
+
+// assign CHARGEPUMP = mprj_io[15];
+ assign analog_out1 = mprj_io[27];
+ assign analog_out2 = mprj_io[28];
+ assign phase_a1_l = mprj_io[23];
+ assign phase_a2_l = mprj_io[19];
+ assign phase_b1_l = mprj_io[16];
+ assign phase_b2_l = mprj_io[20];
+ assign phase_a1_h = mprj_io[21];
+ assign phase_a2_h = mprj_io[18];
+ assign phase_b1_h = mprj_io[14];
+ assign phase_b2_h = mprj_io[17];
+// assign BUFFER_DTR = mprj_io[37];
+// assign MOVE_DONE = mprj_io[24];
+// assign CIPO = mprj_io[36];
+// assign STEPOUTPUT = mprj_io[30];
+// assign DIROUTPUT = mprj_io[31];
+ assign mprj_io[25] = analog_cmp1;
+ assign mprj_io[26] = analog_cmp2;
+// assign mprj_io[18] = ENC_B;
+// assign mprj_io[19] = ENC_A;
+// assign mprj_io[29] = HALT;
+// assign mprj_io[35] = SCK;
+// assign mprj_io[34] = CS;
+// assign mprj_io[22] = COPI;
+ assign mprj_io[32] = step;
+ assign mprj_io[33] = dir;
+ assign resetn = RSTB;
+
+ always @(posedge clock) begin
+ if (!resetn) begin
+ cnt <= 0;
+ analog_cmp1 <= 1;
+ analog_cmp2 <= 1;
+ step <= 1;
+ step_clock <= 40'b0;
+ end
+ else begin
+ cnt <= cnt + 1;
+ enable_in <= 1;
+ if (current1[12] == 1'b1) begin
+ current_abs1 = -current1;
+ end
+ else begin
+ current_abs1 = current1;
+ end
+ if (current2[12] == 1'b1) begin
+ current_abs2 = -current2;
+ end
+ else begin
+ current_abs2 = current2;
+ end
+ step_clock <= step_clock + 1;
+ step <= step_clock[10];
+ analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned
+ analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]);
+ if (cnt <= 20'h4CA9) begin
+ dir <= 1;
+ end
+ else
+ dir <= 0;
+ end
+ end
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
@@ -137,6 +255,7 @@
.resetb (RSTB)
);
+
spiflash #(
.FILENAME("io_ports.hex")
) spiflash (
@@ -148,5 +267,38 @@
.io3() // not used
);
+ pwm_duty duty1(
+ .clk(clock),
+ .resetn(resetn),
+ .pwm(analog_out1),
+ .duty(target_current1)
+ );
+ pwm_duty duty2(
+ .clk(clock),
+ .resetn(resetn),
+ .pwm(analog_out2),
+ .duty(target_current2)
+ );
+ hbridge_coil hbridge_coil1(
+ .clk(clock),
+ .resetn(resetn),
+ .low_1(phase_a1_l),
+ .high_1(phase_a1_h),
+ .low_2(phase_a2_l),
+ .high_2(phase_a2_h),
+ .current(current1),
+ .polarity_invert_config(1'b0)
+ );
+ hbridge_coil hbridge_coil2(
+ .clk(clock),
+ .resetn(resetn),
+ .low_1(phase_b1_l),
+ .high_1(phase_b1_h),
+ .low_2(phase_b2_l),
+ .high_2(phase_b2_h),
+ .current(current2),
+ .polarity_invert_config(1'b0)
+ );
endmodule
`default_nettype wire
+
diff --git a/verilog/rtl/rapcores.v b/verilog/rtl/rapcores.v
index 4f570cf..491d5bd 100644
--- a/verilog/rtl/rapcores.v
+++ b/verilog/rtl/rapcores.v
@@ -22,7 +22,9 @@
`default_nettype none
-module rapcores(
+module rapcores #(
+ parameter BITS = 32
+)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
@@ -57,10 +59,9 @@
output [`MPRJ_IO_PADS-1:0] io_oeb
);
- localparam [6:0] BITS = 32;
-
wire clk;
wire rst;
+ wire enable;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
@@ -91,7 +92,8 @@
assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = wb_clk_i;
- assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+ assign rst = ~la_oen[65] && la_data_in[65] && ~wb_rst_i;
+ assign enable = ~la_oen[64] && la_data_in[64];
// GPIO output enable (0 = output, 1 = input)
assign io_oeb[15] = 1'b0; // CHARGEPUMP
@@ -107,40 +109,52 @@
assign io_oeb[18] = 1'b0; // PHASE_A2_H
assign io_oeb[14] = 1'b0; // PHASE_B1_H
assign io_oeb[17] = 1'b0; // PHASE_B2_H
- assign io_oeb[18] = 1'b1; // ENC_B
- assign io_oeb[19] = 1'b1; // ENC_A
- assign io_oeb[12] = 1'b0; // BUFFER_DTR
+ assign io_oeb[12] = 1'b0; // ENC_B
+ assign io_oeb[13] = 1'b0; // ENC_A
+ assign io_oeb[37] = 1'b0; // BUFFER_DTR
assign io_oeb[24] = 1'b0; // MOVE_DONE
assign io_oeb[29] = 1'b1; // HALT
- assign io_oeb[10] = 1'b1; // SCK
- assign io_oeb[9] = 1'b1; // CS
- assign io_oeb[8] = 1'b1; // COPI
- assign io_oeb[11] = 1'b0; // CIPO
+ assign io_oeb[35] = 1'b1; // SCK
+ assign io_oeb[34] = 1'b1; // CS
+ assign io_oeb[33] = 1'b1; // COPI
+ assign io_oeb[36] = 1'b0; // CIPO
assign io_oeb[30] = 1'b0; // STEPOUTPUT
assign io_oeb[31] = 1'b0; // DIROUTPUT
assign io_oeb[32] = 1'b1; // STEPINPUT
assign io_oeb[33] = 1'b1; // DIRINPUT
// unused
- assign io_oeb[0] = 1'b1; // JTAG I/O
- assign io_oeb[1] = 1'b1; // SDO
- assign io_oeb[2] = 1'b1; // SDI
- assign io_oeb[3] = 1'b1; // CSB
- assign io_oeb[4] = 1'b1; // SCK
- assign io_oeb[5] = 1'b1; // Rx
- assign io_oeb[6] = 1'b1; // Tx
- assign io_oeb[7] = 1'b1; // IRQ
+ assign io_oeb[0] = 1'b0; // JTAG I/O
+ assign io_oeb[1] = 1'b0; // SDO
+ assign io_oeb[2] = 1'b0; // SDI
+ assign io_oeb[3] = 1'b0; // CSB
+ assign io_oeb[4] = 1'b0; // SCK
+ assign io_oeb[5] = 1'b0; // Rx
+ assign io_oeb[6] = 1'b0; // Tx
+ assign io_oeb[7] = 1'b0; // IRQ
assign io_oeb[13] = 1'b1;
- assign io_oeb[22] = 1'b1;
- assign io_oeb[34] = 1'b1;
- assign io_oeb[35] = 1'b1;
- assign io_oeb[36] = 1'b1;
- assign io_oeb[37] = 1'b1;
+ assign io_oeb[8] = 1'b1;
+ assign io_oeb[9] = 1'b1;
+ assign io_oeb[10] = 1'b1;
+ assign io_oeb[11] = 1'b1;
+ assign io_oeb[12] = 1'b1;
+ wire resetn;
+ reg [13:0] resetn_counter = 0;
+ assign resetn = &resetn_counter && rst;
+
+ always @(posedge wb_clk_i) begin
+ if (!resetn && !wb_rst_i && rst) resetn_counter <= resetn_counter +1;
+ end
+
+ // IO
+ assign io_out[7:0] = resetn_counter[13:6]; //count;
+
rapcore rapcore0 (
// IO Pads
.CLK(wb_clk_i),
+ .resetn_in(resetn),
.CHARGEPUMP(io_out[15]),
.analog_cmp1(io_in[25]),
.analog_out1(io_out[27]),
@@ -156,17 +170,18 @@
.PHASE_B2_H(io_out[17]),
.ENC_B(io_in[18]),
.ENC_A(io_in[19]),
- .BUFFER_DTR(io_out[12]),
+ .BUFFER_DTR(io_out[37]),
.MOVE_DONE(io_out[24]),
.HALT(io_in[29]),
- .SCK(io_in[10]),
- .CS(io_in[9]),
- .COPI(io_in[8]),
- .CIPO(io_out[11]),
+ .SCK(io_in[35]),
+ .CS(io_in[34]),
+ .COPI(io_in[22]),
+ .CIPO(io_out[36]),
.STEPOUTPUT(io_out[30]),
.DIROUTPUT(io_out[31]),
.STEPINPUT(io_in[32]),
- .DIRINPUT(io_in[33])
+ .DIRINPUT(io_in[33]),
+ .ENINPUT(enable)
);
endmodule
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index e8cc151..44e8eda 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -78,7 +78,7 @@
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
- wire [31:0] rdata;
+ wire [31:0] rdata;
wire [31:0] wdata;
wire [BITS-1:0] count;
@@ -87,7 +87,7 @@
wire [31:0] la_write;
// WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
+ assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;
@@ -98,41 +98,75 @@
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
+ // Assuming LA probes [63:32] are for controlling the count register
assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = wb_clk_i;
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
-
- top top (
-
- // IO Pads
- .CLK(clk),
- .CHARGEPUMP(io_out[15]),
- .analog_cmp1(io_in[25]),
- .analog_out1(io_out[27]),
- .analog_cmp2(io_in[26]),
- .analog_out2(io_out[28]),
- .PHASE_A1(io_out[23]),
- .PHASE_A2(io_out[19]),
- .PHASE_B1(io_out[16]),
- .PHASE_B2(io_out[20]),
- .PHASE_A1_H(io_out[21]),
- .PHASE_A2_H(io_out[18]),
- .PHASE_B1_H(io_out[14]),
- .PHASE_B2_H(io_out[17]),
- .ENC_B(io_in[18]),
- .ENC_A(io_in[19]),
- .BUFFER_DTR(io_out[12]),
- .MOVE_DONE(io_out[24]),
- .HALT(io_in[29]),
- .SCK(io_in[10]),
- .CS(io_in[9]),
- .COPI(io_in[8]),
- .CIPO(io_out[11])
+ counter #(
+ .BITS(BITS)
+ ) counter(
+ .clk(clk),
+ .reset(rst),
+ .ready(wbs_ack_o),
+ .valid(valid),
+ .rdata(rdata),
+ .wdata(wbs_dat_i),
+ .wstrb(wstrb),
+ .la_write(la_write),
+ .la_input(la_data_in[63:32]),
+ .count(count)
);
endmodule
+module counter #(
+ parameter BITS = 32
+)(
+ input clk,
+ input reset,
+ input valid,
+ input [3:0] wstrb,
+ input [BITS-1:0] wdata,
+ input [BITS-1:0] la_write,
+ input [BITS-1:0] la_input,
+ output ready,
+ output [BITS-1:0] rdata,
+ output [BITS-1:0] count
+);
+ reg ready;
+ reg [BITS-1:0] count;
+ reg [BITS-1:0] rdata;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 0;
+ ready <= 0;
+ end else begin
+ ready <= 1'b0;
+ if (~|la_write) begin
+ count <= count + 1;
+ end
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ rdata <= count;
+ if (wstrb[0]) count[7:0] <= wdata[7:0];
+ if (wstrb[1]) count[15:8] <= wdata[15:8];
+ if (wstrb[2]) count[23:16] <= wdata[23:16];
+ if (wstrb[3]) count[31:24] <= wdata[31:24];
+ end
+ end
+ end
+
+ genvar i;
+ generate
+ for(i=0; i<BITS; i=i+1) begin
+ always @(posedge clk) begin
+ if (la_write[i]) count[i] <= la_input[i];
+ end
+ end
+ endgenerate
+
+endmodule
`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0807133..9de1bc4 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -79,7 +79,9 @@
/* User project is instantiated here */
/*--------------------------------------*/
- rapcores rapcores0 (
+ rapcore_caravel rapcore_caravel0 (
+
+`ifndef SIM
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
@@ -90,7 +92,7 @@
.vssd1(vssd1), // User area 1 digital ground
.vssd2(vssd2), // User area 2 digital ground
`endif
-
+`endif
// MGMT core clock and reset
.wb_clk_i(wb_clk_i),
