temp cv tb hack
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index c9c962b..b6e1d4f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -65,6 +65,8 @@
/*--------------------------------------*/
rapcores rapcores0 (
+
+`ifndef SIM
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power
@@ -75,7 +77,7 @@
.vssd1(vssd1), // User area 1 digital ground
.vssd2(vssd2), // User area 2 digital ground
`endif
-
+`endif
// MGMT core clock and reset
.wb_clk_i(wb_clk_i),
