Merge branch 'develop' of github.com:efabless/caravel into sjk/mergewdevelop1
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..b2e43ea
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+pdk_root
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..489a9cf
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,6 @@
+[submodule "rapcores"]
+ path = rapcores
+ url = https://github.com/RAPcores/rapcores.git
+[submodule "openlane_repo"]
+ path = openlane_repo
+ url = https://github.com/RAPcores/openlane.git
diff --git a/INSTALL.md b/INSTALL.md
new file mode 100644
index 0000000..755b9ac
--- /dev/null
+++ b/INSTALL.md
@@ -0,0 +1,46 @@
+# RAPCore Caravel Flow
+
+Notes on the Caravel flow:
+
+prereqs (Ubuntu):
+
+`sudo apt install tcl-dev tk-dev csh`
+
+Install magic (this ends up global on the system):
+
+```
+git clone https://github.com/RTimothyEdwards/magic.git
+cd magic
+./configure [options]
+make
+make install
+```
+
+Install Docker:
+
+https://www.digitalocean.com/community/tutorials/how-to-install-and-use-docker-on-ubuntu-20-04
+
+
+
+Run the openlane script:
+
+```
+./openlane.sh
+```
+
+This will pull openlane (which pulls skywater_pdk and open_pdks).
+
+Run caravel:
+
+```
+./caravel.sh
+```
+```
+./caravel.sh
+```
+
+Open .mag to see the design:
+
+```
+steve@sjkdsk1:~/Ultimachine/rapcore_caravel_flow/caravel/openlane/user_proj_example/runs/user_proj_example/results/magic (master=)$ magic -T sky130A user_proj_example.mag
+```
diff --git a/LICENSE b/LICENSE
index d645695..e720327 100644
--- a/LICENSE
+++ b/LICENSE
@@ -187,7 +187,7 @@
same "printed page" as the copyright notice for easier
identification within third-party archives.
- Copyright [yyyy] [name of copyright owner]
+ Copyright 2020 RAPcore Developers
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/README.md b/README.md
index 9679858..5bfd9fb 100644
--- a/README.md
+++ b/README.md
@@ -1,71 +1,28 @@
-# CIIC Harness
+# RAPcore Caravel Flow
-A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
+https://rapcores.github.io/rapcores/
-<p align=”center”>
-<img src="/doc/ciic_harness.png" width="75%" height="75%">
-</p>
+The Robotic Application Processing Core on the OpenMPW/Caravel Shuttle run sponsored by Google .
-## Getting Started:
+RAPcore is a project targeting FPGAs and ASIC devices for the next generation of motor and motion
+control applications. It is a peripheral that sits between firmwares and motors to free up
+processing on the microcontroller and greatly simplify the motor driver.
-Start by cloning the repo and uncompressing the files.
-```bash
-git clone https://github.com/efabless/caravel.git
-cd caravel
-make uncompress
-```
+## Features
-Install the required version of the PDK by running the following commands:
+- Onboard stepper motor commutator with microstepping
+- Fixed Point Step-Timing Algorithm
+- High-speed Quadrature Encoder Accumulator
+- High-Speed SPI Bus
-```bash
-export PDK_ROOT=<The place where you want to install the pdk>
-make pdk
-```
+## Build Requirements
-Then, you can learn more about the caravel chip by watching these video:
-- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
-- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
-- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
+See INSTALL.md for local development instructions.
-## Aboard Caravel:
+## Documentation
-Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
+https://rapcores.github.io/rapcores/
-If you will use OpenLANE to harden your design, go through the instructions in this [README.md][0].
+## License
-Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
-
-- Magic installed on your machine. We may provide a Dockerized version later.
-- You have your user_project_wrapper.gds under `./gds/` in the Caravel directory.
-
-Run the following command:
-
-```bash
-export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step>
-make
-```
-
-This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
-
-## Managment SoC
-The managment SoC runs firmware that can be used to:
-- Configure User Project I/O pads
-- Observe and control User Project signals (through on-chip logic analyzer probes)
-- Control the User Project power supply
-
-The memory map of the management SoC can be found [here](verilog/rtl/README)
-
-## User Project Area
-This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel_datasheet.pdf) for details.
-The repository contains a [sample user project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>
-
-<p align=”center”>
-<img src="/doc/counter_32.png" width="50%" height="50%">
-</p>
-
-The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the User Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
-2. Configure the User Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
-3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
-
-[0]: openlane/README.md
+[ISC License](https://en.wikipedia.org/wiki/ISC_license).
diff --git a/caravel.sh b/caravel.sh
new file mode 100755
index 0000000..93d859e
--- /dev/null
+++ b/caravel.sh
@@ -0,0 +1,8 @@
+#! /usr/bin/env bash
+
+export PDK_ROOT=`pwd`/pdk_root
+export OPENLANE_ROOT=`pwd`/openlane_repo
+echo $PDK_ROOT
+echo $OPENLANE_ROOT
+cd openlane
+make rapcore OPENLANE_IMAGE_NAME=openlane:rc5
diff --git a/clean.sh b/clean.sh
new file mode 100755
index 0000000..79809df
--- /dev/null
+++ b/clean.sh
@@ -0,0 +1,3 @@
+#! /usr/bin/env bash
+
+rm -rf openlane caravel pdk_root
diff --git a/info.yaml b/info.yaml
index ffd0520..3322145 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,18 +1,19 @@
----
-project:
- description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+---
+project:
+ description: "RAPcore motor and motion controller on the Google sponsored Open MPW shuttles for SKY130."
foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
+ git_url: "https://github.com/RAPcores/rapcore_caravel_flow"
+ organization: "RAPcore"
+ organization_url: "http://rapcores.org"
+ owner: "RAPcore developers"
process: "SKY130"
- project_name: "Caravel"
- tags:
+ project_name: "rapcore"
+ tags:
- "Open MPW"
- "Test Harness"
+ - "Motor Control"
category: "Test Harness"
top_level_netlist: "verilog/rtl/caravel.v"
- user_level_netlist: "verilog/gl/user_project_wrapper.v"
+ user_level_netlist: "verilog/gl/rapcore.v"
version: "1.00"
cover_image: "doc/ciic_harness.png"
diff --git a/openlane.sh b/openlane.sh
new file mode 100755
index 0000000..d8c4609
--- /dev/null
+++ b/openlane.sh
@@ -0,0 +1,12 @@
+#! /usr/bin/env bash
+
+# build openlane
+mkdir -p pdk_root
+export PDK_ROOT=`pwd`/pdk_root
+git submodule init
+cd openlane_repo
+make
+cd docker_build
+make merge
+cd ../..
+chmod +x openlane_repo/scripts/*
diff --git a/openlane/rapcore/config.tcl b/openlane/rapcore/config.tcl
new file mode 100644
index 0000000..e2532f4
--- /dev/null
+++ b/openlane/rapcore/config.tcl
@@ -0,0 +1,35 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) rapcore
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../rapcores/src/constants.v \
+ $script_dir/../../rapcore_caravel_defines.v \
+ $script_dir/../../rapcores/src/macro_params.v \
+ $script_dir/../../rapcores/src/top.v \
+ $script_dir/../../verilog/rtl/rapcore.v \
+ $script_dir/../../rapcores/src/stepper.v \
+ $script_dir/../../rapcores/src/spi.v \
+ $script_dir/../../rapcores/src/quad_enc.v \
+ $script_dir/../../rapcores/src/pwm.v \
+ $script_dir/../../rapcores/src/microstepper/microstepper_top.v \
+ $script_dir/../../rapcores/src/microstepper/microstep_counter.v \
+ $script_dir/../../rapcores/src/microstepper/cosine.v \
+ $script_dir/../../rapcores/src/microstepper/analog_out.v \
+ $script_dir/../../rapcores/src/microstepper/chargepump.v \
+ $script_dir/../../rapcores/src/microstepper/mytimer.v"
+
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2500 3500"
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+# set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
+# set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
+
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.01
diff --git a/openlane/rapcore/pin_order.cfg b/openlane/rapcore/pin_order.cfg
new file mode 100644
index 0000000..8128f78
--- /dev/null
+++ b/openlane/rapcore/pin_order.cfg
@@ -0,0 +1,9 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+
+#N
+io_.*
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index ca6d3e9..15344f4 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -3,15 +3,28 @@
set ::env(DESIGN_NAME) user_proj_example
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ $script_dir/../../verilog/rtl/defines.v \
+ $script_dir/../../rapcores/src/constants.v \
+ $script_dir/../../rapcore_caravel_defines.v \
+ $script_dir/../../rapcores/src/macro_params.v \
+ $script_dir/../../rapcores/src/top.v \
+ $script_dir/../../verilog/rtl/user_proj_example.v \
+ $script_dir/../../rapcores/src/stepper.v \
+ $script_dir/../../rapcores/src/spi.v \
+ $script_dir/../../rapcores/src/quad_enc.v \
+ $script_dir/../../rapcores/src/pwm.v \
+ $script_dir/../../rapcores/src/microstepper/microstepper_top.v \
+ $script_dir/../../rapcores/src/microstepper/microstep_counter.v \
+ $script_dir/../../rapcores/src/microstepper/cosine.v \
+ $script_dir/../../rapcores/src/microstepper/analog_out.v \
+ $script_dir/../../rapcores/src/microstepper/chargepump.v \
+ $script_dir/../../rapcores/src/microstepper/mytimer.v"
-set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 600 600"
+set ::env(DIE_AREA) "0 0 2500 3500"
set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -19,4 +32,4 @@
# set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.15
+set ::env(PL_TARGET_DENSITY) 0.01
diff --git a/openlane_repo b/openlane_repo
new file mode 160000
index 0000000..7e43f72
--- /dev/null
+++ b/openlane_repo
@@ -0,0 +1 @@
+Subproject commit 7e43f72450dbfb968610f150be646628e65d3d2f
diff --git a/precheck.sh b/precheck.sh
new file mode 100755
index 0000000..9eaeb5d
--- /dev/null
+++ b/precheck.sh
@@ -0,0 +1,10 @@
+#! /usr/bin/env bash
+
+git clone git@github.com:efabless/open_mpw_precheck.git
+cd open_mpw_precheck/dependencies
+sh build-docker.sh
+cd ..
+export TARGET_PATH=`pwd`/..
+docker run -it -v $(pwd):/usr/local/bin \
+ -u $(id -u $USER):$(id -g $USER) -v $TARGET_PATH:$TARGET_PATH \
+ open_mpw_prechecker:latest python3 open_mpw_prechecker.py -t $TARGET_PATH
diff --git a/rapcore_caravel_defines.v b/rapcore_caravel_defines.v
new file mode 100644
index 0000000..c63166f
--- /dev/null
+++ b/rapcore_caravel_defines.v
@@ -0,0 +1,31 @@
+
+// Enable SPI Interface
+`define SPI_INTERFACE
+
+// Use PLL for higher SPI frequencies
+//`define SPIPLL
+
+// Enable Buffer DTR pin
+`define BUFFER_DTR
+
+// Enable Move Done Pin
+`define MOVE_DONE
+
+// Enable Halt Input
+`define HALT
+
+// Motor Definitions
+//`define DUAL_HBRIDGE 1
+`define ULTIBRIDGE 1
+
+// Encoder Count
+`define QUAD_ENC 1
+
+// External Step/DIR Input
+`define STEPINPUT
+
+// Output Step/DIR signals
+`define STEPOUTPUT
+
+// Change the Move Buffer Size. Should be power of two
+//`define MOVE_BUFFER_SIZE 4
diff --git a/rapcores b/rapcores
new file mode 160000
index 0000000..57bf611
--- /dev/null
+++ b/rapcores
@@ -0,0 +1 @@
+Subproject commit 57bf61140f661a076419f6225a2cef898b3bd152
diff --git a/verilog/rtl/rapcore.v b/verilog/rtl/rapcore.v
new file mode 100644
index 0000000..d976d7a
--- /dev/null
+++ b/verilog/rtl/rapcore.v
@@ -0,0 +1,123 @@
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only). The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project. The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module rapcore #(
+ parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oen,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb
+);
+ wire clk;
+ wire rst;
+
+ wire [`MPRJ_IO_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+ wire [31:0] rdata;
+ wire [31:0] wdata;
+ wire [BITS-1:0] count;
+
+ wire valid;
+ wire [3:0] wstrb;
+ wire [31:0] la_write;
+
+ // WB MI A
+ assign valid = wbs_cyc_i && wbs_stb_i;
+ assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ assign wbs_dat_o = rdata;
+ assign wdata = wbs_dat_i;
+
+ // IO
+ //assign io_out = count;
+ //assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+
+ // LA
+ assign la_data_out = {{(127-BITS){1'b0}}, count};
+ // Assuming LA probes [63:32] are for controlling the count register
+ assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = wb_clk_i;
+ assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+
+
+ top top (
+
+ // IO Pads
+ .CLK(clk),
+ .CHARGEPUMP(io_out[15]),
+ .analog_cmp1(io_in[25]),
+ .analog_out1(io_out[27]),
+ .analog_cmp2(io_in[26]),
+ .analog_out2(io_out[28]),
+ .PHASE_A1(io_out[23]),
+ .PHASE_A2(io_out[19]),
+ .PHASE_B1(io_out[16]),
+ .PHASE_B2(io_out[20]),
+ .PHASE_A1_H(io_out[21]),
+ .PHASE_A2_H(io_out[18]),
+ .PHASE_B1_H(io_out[14]),
+ .PHASE_B2_H(io_out[17]),
+ .ENC_B(io_in[18]),
+ .ENC_A(io_in[19]),
+ .BUFFER_DTR(io_out[12]),
+ .MOVE_DONE(io_out[24]),
+ .HALT(io_in[29]),
+ .SCK(io_in[10]),
+ .CS(io_in[9]),
+ .COPI(io_in[8]),
+ .CIPO(io_out[11])
+ );
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 3445aa0..89d09b8 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -63,7 +63,7 @@
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
- wire [31:0] rdata;
+ wire [31:0] rdata;
wire [31:0] wdata;
wire [BITS-1:0] count;
@@ -72,7 +72,7 @@
wire [31:0] la_write;
// WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
+ assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;
@@ -83,75 +83,41 @@
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
+ // Assuming LA probes [63:32] are for controlling the count register
assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = wb_clk_i;
assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
+
+ top top (
+
+ // IO Pads
+ .CLK(clk),
+ .CHARGEPUMP(io_out[15]),
+ .analog_cmp1(io_in[25]),
+ .analog_out1(io_out[27]),
+ .analog_cmp2(io_in[26]),
+ .analog_out2(io_out[28]),
+ .PHASE_A1(io_out[23]),
+ .PHASE_A2(io_out[19]),
+ .PHASE_B1(io_out[16]),
+ .PHASE_B2(io_out[20]),
+ .PHASE_A1_H(io_out[21]),
+ .PHASE_A2_H(io_out[18]),
+ .PHASE_B1_H(io_out[14]),
+ .PHASE_B2_H(io_out[17]),
+ .ENC_B(io_in[18]),
+ .ENC_A(io_in[19]),
+ .BUFFER_DTR(io_out[12]),
+ .MOVE_DONE(io_out[24]),
+ .HALT(io_in[29]),
+ .SCK(io_in[10]),
+ .CS(io_in[9]),
+ .COPI(io_in[8]),
+ .CIPO(io_out[11])
);
endmodule
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end
- end
- end
-
- genvar i;
- generate
- for(i=0; i<BITS; i=i+1) begin
- always @(posedge clk) begin
- if (la_write[i]) count[i] <= la_input[i];
- end
- end
- endgenerate
-
-endmodule
`default_nettype wire
