| commit | c941188321f73b10402a6a141675e5eda9f80c03 | [log] [tgz] |
|---|---|---|
| author | agorararmard <aagouhar@efabless.com> | Tue Dec 01 01:37:05 2020 +0200 |
| committer | agorararmard <aagouhar@efabless.com> | Tue Dec 01 01:37:05 2020 +0200 |
| tree | f012449939ac1e1bb2ec2900eb07cde2b09ea42b | |
| parent | 94d61b49b0dad97e1a2cdf5a035e6fe8c62b456d [diff] [blame] |
[DATA] updated caravel.synthesis.v under verilog/gl and update info.yaml
diff --git a/info.yaml b/info.yaml index ffd0520..db9146e 100644 --- a/info.yaml +++ b/info.yaml
@@ -12,7 +12,7 @@ - "Open MPW" - "Test Harness" category: "Test Harness" - top_level_netlist: "verilog/rtl/caravel.v" + top_level_netlist: "verilog/gl/caravel.synthesis.v" user_level_netlist: "verilog/gl/user_project_wrapper.v" version: "1.00" cover_image: "doc/ciic_harness.png"