commit c5a82310c484236c3222bd5536d7f3e86bab207f
author Steve Kelly <kd2cca@gmail.com> Sun Nov 29 00:42:16 2020 -0500
committer Steve Kelly <kd2cca@gmail.com> Sun Nov 29 00:42:16 2020 -0500
tree 5e42706dbd81575039213ef8e634712b6f31517c
parent 9175d1997d9f5ee1d65228f03a2ca5c6d0771204

no fancy clock

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 904bc71..89d09b8 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -86,7 +86,7 @@
     // Assuming LA probes [63:32] are for controlling the count register
     assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
     // Assuming LA probes [65:64] are for controlling the count clk & reset
-    assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
+    assign clk = wb_clk_i;
     assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;