commit bb9d8592c5b60a6da9b2ef46048585eea91670cd
author Steve Kelly <kd2cca@gmail.com> Fri Dec 18 22:37:46 2020 -0500
committer Steve Kelly <kd2cca@gmail.com> Fri Dec 18 22:37:46 2020 -0500
tree 3087c9bd50c0c652d7f4ca690bff38f9553dbd7d
parent 3289c6497ad434b20c406324edb216a506dd28b7

use external enable pins

verilog/rtl/rapcores.v

diff --git a/verilog/rtl/rapcores.v b/verilog/rtl/rapcores.v
index 8d31863..b1d46d6 100644
--- a/verilog/rtl/rapcores.v
+++ b/verilog/rtl/rapcores.v
@@ -122,6 +122,8 @@
     assign io_oeb[31] = 1'b0;    // DIROUTPUT
     assign io_oeb[32] = 1'b1;    // STEPINPUT
     assign io_oeb[33] = 1'b1;    // DIRINPUT
+    assign io_oeb[11] = 1'b1;    // ENINPUT
+    assign io_oeb[10] = 1'b0;    // ENOUTPUT
     // unused
     assign io_oeb[0] = 1'b0;    // JTAG I/O
     assign io_oeb[1] = 1'b0;    // SDO
@@ -133,7 +135,6 @@
     assign io_oeb[7] = 1'b0;    // IRQ
     assign io_oeb[8] = 1'b1;
     assign io_oeb[9] = 1'b1;
-    assign io_oeb[10] = 1'b1;
 
 
     wire resetn;
@@ -178,7 +179,8 @@
         .DIROUTPUT(io_out[31]),
         .STEPINPUT(io_in[32]),
         .DIRINPUT(io_in[33]),
-        .ENINPUT(enable)
+        .ENINPUT(io_in[11]),
+        .ENOUTPUT(io_out[10])
     );
 
 endmodule