sim fixes. revert to original proj example.
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index 3ab6272..220a1d2 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -1,11 +1,15 @@
FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
RTL_PATH = ../../../../rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
+RAPCORES_PATH = ../../../../../rapcores
-GCC_PATH?=/ef/apps/bin
+GCC_PATH?=//opt/riscv32/bin
GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+SIM?=RTL
.SUFFIXES:
@@ -16,9 +20,16 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
-o $@ $<
+else
+ iverilog -DPROJ_GL -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
+ -o $@ $<
+endif
+
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 63b7c93..bbc2390 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -2,6 +2,32 @@
`timescale 1 ns / 1 ps
+`include "defines.v"
+`include "rapcore_caravel_defines.v"
+`include "macro_params.v"
+`include "constants.v"
+`include "quad_enc.v"
+`include "spi.v"
+`include "dda_timer.v"
+`include "spi_state_machine.v"
+`include "microstepper/chargepump.v"
+`include "microstepper/microstepper_control.v"
+`include "microstepper/mytimer_8.v"
+`include "microstepper/mytimer_10.v"
+`include "microstepper/microstep_counter.v"
+`include "microstepper/cosine.v"
+`include "microstepper/analog_out.v"
+`include "microstepper/microstepper_top.v"
+`include "rapcore.v"
+
+//`define USE_POWER_PINS
+
+`ifdef PROJ_GL
+ `include "gl/rapcore.v"
+`else
+ `include "rapcore_caravel.v"
+`endif
+
`include "caravel.v"
`include "spiflash.v"
diff --git a/verilog/rtl/rapcore.v b/verilog/rtl/rapcore.v
deleted file mode 100644
index d976d7a..0000000
--- a/verilog/rtl/rapcore.v
+++ /dev/null
@@ -1,123 +0,0 @@
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_proj_example
- *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only). The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project. The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
- *
- *-------------------------------------------------------------
- */
-
-module rapcore #(
- parameter BITS = 32
-)(
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oen,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb
-);
- wire clk;
- wire rst;
-
- wire [`MPRJ_IO_PADS-1:0] io_in;
- wire [`MPRJ_IO_PADS-1:0] io_out;
- wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
-
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- //assign io_out = count;
- //assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
-
- // LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = wb_clk_i;
- assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
-
-
- top top (
-
- // IO Pads
- .CLK(clk),
- .CHARGEPUMP(io_out[15]),
- .analog_cmp1(io_in[25]),
- .analog_out1(io_out[27]),
- .analog_cmp2(io_in[26]),
- .analog_out2(io_out[28]),
- .PHASE_A1(io_out[23]),
- .PHASE_A2(io_out[19]),
- .PHASE_B1(io_out[16]),
- .PHASE_B2(io_out[20]),
- .PHASE_A1_H(io_out[21]),
- .PHASE_A2_H(io_out[18]),
- .PHASE_B1_H(io_out[14]),
- .PHASE_B2_H(io_out[17]),
- .ENC_B(io_in[18]),
- .ENC_A(io_in[19]),
- .BUFFER_DTR(io_out[12]),
- .MOVE_DONE(io_out[24]),
- .HALT(io_in[29]),
- .SCK(io_in[10]),
- .CS(io_in[9]),
- .COPI(io_in[8]),
- .CIPO(io_out[11])
- );
-
-endmodule
-
-`default_nettype wire
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 89d09b8..3445aa0 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -63,7 +63,7 @@
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
- wire [31:0] rdata;
+ wire [31:0] rdata;
wire [31:0] wdata;
wire [BITS-1:0] count;
@@ -72,7 +72,7 @@
wire [31:0] la_write;
// WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
+ assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;
@@ -83,41 +83,75 @@
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
+ // Assuming LA probes [63:32] are for controlling the count register
assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = wb_clk_i;
+ // Assuming LA probes [65:64] are for controlling the count clk & reset
+ assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
-
- top top (
-
- // IO Pads
- .CLK(clk),
- .CHARGEPUMP(io_out[15]),
- .analog_cmp1(io_in[25]),
- .analog_out1(io_out[27]),
- .analog_cmp2(io_in[26]),
- .analog_out2(io_out[28]),
- .PHASE_A1(io_out[23]),
- .PHASE_A2(io_out[19]),
- .PHASE_B1(io_out[16]),
- .PHASE_B2(io_out[20]),
- .PHASE_A1_H(io_out[21]),
- .PHASE_A2_H(io_out[18]),
- .PHASE_B1_H(io_out[14]),
- .PHASE_B2_H(io_out[17]),
- .ENC_B(io_in[18]),
- .ENC_A(io_in[19]),
- .BUFFER_DTR(io_out[12]),
- .MOVE_DONE(io_out[24]),
- .HALT(io_in[29]),
- .SCK(io_in[10]),
- .CS(io_in[9]),
- .COPI(io_in[8]),
- .CIPO(io_out[11])
+ counter #(
+ .BITS(BITS)
+ ) counter(
+ .clk(clk),
+ .reset(rst),
+ .ready(wbs_ack_o),
+ .valid(valid),
+ .rdata(rdata),
+ .wdata(wbs_dat_i),
+ .wstrb(wstrb),
+ .la_write(la_write),
+ .la_input(la_data_in[63:32]),
+ .count(count)
);
endmodule
+module counter #(
+ parameter BITS = 32
+)(
+ input clk,
+ input reset,
+ input valid,
+ input [3:0] wstrb,
+ input [BITS-1:0] wdata,
+ input [BITS-1:0] la_write,
+ input [BITS-1:0] la_input,
+ output ready,
+ output [BITS-1:0] rdata,
+ output [BITS-1:0] count
+);
+ reg ready;
+ reg [BITS-1:0] count;
+ reg [BITS-1:0] rdata;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 0;
+ ready <= 0;
+ end else begin
+ ready <= 1'b0;
+ if (~|la_write) begin
+ count <= count + 1;
+ end
+ if (valid && !ready) begin
+ ready <= 1'b1;
+ rdata <= count;
+ if (wstrb[0]) count[7:0] <= wdata[7:0];
+ if (wstrb[1]) count[15:8] <= wdata[15:8];
+ if (wstrb[2]) count[23:16] <= wdata[23:16];
+ if (wstrb[3]) count[31:24] <= wdata[31:24];
+ end
+ end
+ end
+
+ genvar i;
+ generate
+ for(i=0; i<BITS; i=i+1) begin
+ always @(posedge clk) begin
+ if (la_write[i]) count[i] <= la_input[i];
+ end
+ end
+ endgenerate
+
+endmodule
`default_nettype wire
