tb wip
diff --git a/rapcores b/rapcores
index b7587ab..af0fa8a 160000
--- a/rapcores
+++ b/rapcores
@@ -1 +1 @@
-Subproject commit b7587ab780f9b5c5c3a264019ab4ee1e8c0964fd
+Subproject commit af0fa8a9764b66a8737bf6f1ab3b89956ffd4c71
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index 2f91b86..8237f6f 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -1,4 +1,5 @@
FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
RTL_PATH = ../../../../rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -21,16 +22,14 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
- -I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src -I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \
-o $@ $<
else
- iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) -I $(RAPCORES_PATH)/boards \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(VERILOG_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
- -I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \
- $< -o $@
+ iverilog -DPROJ_GL -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
+ -o $@ $<
endif
-# MERGE: -I $(VERILOG_PATH) maybe needed for GL
+
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
index add8845..19c3652 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -8,7 +8,7 @@
void main()
{
- /*
+ /*
IO Control Registers
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
@@ -16,8 +16,8 @@
Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
+
+
Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
@@ -65,7 +65,7 @@
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
// Configure LA probes [63:32] as outputs from the cpu
reg_la0_ena = 0xFFFFFFFF; // [31:0]
reg_la1_ena = 0x00000000; // [95:64]
@@ -76,4 +76,3 @@
reg_la2_data = 0x00000003;
}
-
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.hex b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.hex
new file mode 100755
index 0000000..246493d
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.hex
@@ -0,0 +1,56 @@
+@00000000
+81 40 81 41 01 42 81 42 01 43 81 43 01 44 81 44
+01 45 81 45 01 46 81 46 01 47 81 47 01 48 81 48
+01 49 81 49 01 4A 81 4A 01 4B 81 4B 01 4C 81 4C
+01 4D 81 4D 01 4E 81 4E 01 4F 81 4F 17 05 00 00
+13 05 45 33 93 05 00 00 13 06 00 00 63 D8 C5 00
+14 41 94 C1 11 05 91 05 E3 CC C5 FE 13 05 00 00
+93 05 00 00 63 57 B5 00 23 20 05 00 11 05 E3 4D
+B5 FE 71 28 01 A0 01 00 B7 02 00 28 13 03 00 12
+23 90 62 00 A3 81 02 00 05 C6 21 4F 93 73 F6 0F
+93 DE 73 00 23 80 D2 01 93 EE 0E 01 23 80 D2 01
+86 03 93 F3 F3 0F 7D 1F E3 14 0F FE 23 80 62 00
+A1 C9 13 0F 00 02 83 23 05 00 A1 4F 93 DE F3 01
+23 80 D2 01 93 EE 0E 01 23 80 D2 01 83 CE 02 00
+93 FE 2E 00 93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F
+63 17 0F 00 23 20 75 00 11 05 83 23 05 00 FD 1F
+E3 96 0F FC FD 15 F1 F1 63 04 0F 00 23 20 75 00
+13 03 00 08 A3 81 62 00 82 80 01 00 00 00 41 11
+22 C6 00 08 B7 07 00 26 93 87 07 02 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 47 02 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 87 02 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 C7 02 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 07 03 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 47 03 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 87 03 13 07 20 40
+98 C3 B7 07 00 26 93 87 C7 03 13 07 20 40 98 C3
+B7 07 00 26 93 87 C7 05 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 07 06 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 87 05 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 C7 05 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 07 06 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 47 06 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 87 06 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 C7 06 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 07 07 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 47 07 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 87 07 13 07 20 40 98 C3 B7 07
+00 26 93 87 C7 07 09 67 13 07 87 80 98 C3 B7 07
+00 26 93 87 07 08 09 67 13 07 87 80 98 C3 B7 07
+00 26 93 87 47 08 13 07 20 40 98 C3 B7 07 00 26
+93 87 87 08 13 07 20 40 98 C3 B7 07 00 26 93 87
+C7 08 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87
+07 09 09 67 13 07 87 80 98 C3 B7 07 00 26 93 87
+47 09 13 07 20 40 98 C3 B7 07 00 26 93 87 87 09
+09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 09
+09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 07 0A
+13 07 20 40 98 C3 B7 07 00 26 93 87 47 0A 13 07
+20 40 98 C3 B7 07 00 26 93 87 87 0A 13 07 20 40
+98 C3 B7 07 00 26 93 87 C7 0A 13 07 20 40 98 C3
+B7 07 00 26 93 87 07 0B 09 67 13 07 87 80 98 C3
+B7 07 00 26 93 87 47 0B 09 67 13 07 87 80 98 C3
+B7 07 00 26 05 47 98 C3 01 00 B7 07 00 26 98 43
+85 47 E3 0C F7 FE B7 07 00 25 C1 07 7D 57 98 C3
+B7 07 00 25 D1 07 23 A0 07 00 B7 07 00 25 E1 07
+23 A0 07 00 B7 07 00 25 F1 07 7D 57 98 C3 B7 07
+00 25 A1 07 0D 47 98 C3 01 00 32 44 41 01 82 80
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.vvp b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.vvp
new file mode 100755
index 0000000..07064c5
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.vvp
Binary files differ
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 5148a69..79aaa81 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -2,9 +2,6 @@
`timescale 1 ns / 1 ps
-//`define USE_POWER_PINS
-
-
`include "defines.v"
`include "mpw_one_defines.v"
`include "macro_params.v"
@@ -24,9 +21,12 @@
`include "rapcore.v"
`include "hbridge_coil.v"
`include "pwm_duty.v"
+`include "rapcore_harness_tb.v"
-`ifdef GL
- `include "gl/rapcores.v"
+//`define USE_POWER_PINS
+
+`ifdef PROJ_GL
+ `include "gl/rapcore.v"
`else
`include "rapcores.v"
`endif
@@ -135,86 +135,40 @@
wire signed [12:0] current1;
wire signed [12:0] current2;
- wire analog_out1;
- wire analog_out2;
- reg analog_cmp1;
- reg analog_cmp2;
- reg [40:0] step_clock;
- reg [20:0] cnt;
- reg [12:0] current_abs1;
- reg [12:0] current_abs2;
- wire phase_a1_l;
- wire phase_a2_l;
- wire phase_b1_l;
- wire phase_b2_l;
- wire phase_a1_h;
- wire phase_a2_h;
- wire phase_b1_h;
- wire phase_b2_h;
- wire resetn;
+ //assign resetn = RSTB;
-// assign CHARGEPUMP = mprj_io[15];
- assign analog_out1 = mprj_io[27];
- assign analog_out2 = mprj_io[28];
- assign phase_a1_l = mprj_io[23];
- assign phase_a2_l = mprj_io[19];
- assign phase_b1_l = mprj_io[16];
- assign phase_b2_l = mprj_io[20];
- assign phase_a1_h = mprj_io[21];
- assign phase_a2_h = mprj_io[18];
- assign phase_b1_h = mprj_io[14];
- assign phase_b2_h = mprj_io[17];
-// assign BUFFER_DTR = mprj_io[37];
-// assign MOVE_DONE = mprj_io[24];
-// assign CIPO = mprj_io[36];
-// assign STEPOUTPUT = mprj_io[30];
-// assign DIROUTPUT = mprj_io[31];
- assign mprj_io[25] = analog_cmp1;
- assign mprj_io[26] = analog_cmp2;
-// assign mprj_io[18] = ENC_B;
-// assign mprj_io[19] = ENC_A;
-// assign mprj_io[29] = HALT;
-// assign mprj_io[35] = SCK;
-// assign mprj_io[34] = CS;
-// assign mprj_io[22] = COPI;
- assign mprj_io[32] = step;
- assign mprj_io[33] = dir;
- assign resetn = RSTB;
-
- always @(posedge clock) begin
- if (!resetn) begin
- cnt <= 0;
- analog_cmp1 <= 1;
- analog_cmp2 <= 1;
- step <= 1;
- step_clock <= 40'b0;
- end
- else begin
- cnt <= cnt + 1;
- enable_in <= 1;
- if (current1[12] == 1'b1) begin
- current_abs1 = -current1;
- end
- else begin
- current_abs1 = current1;
- end
- if (current2[12] == 1'b1) begin
- current_abs2 = -current2;
- end
- else begin
- current_abs2 = current2;
- end
- step_clock <= step_clock + 1;
- step <= step_clock[10];
- analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned
- analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]);
- if (cnt <= 20'hC400) begin
- dir <= 1;
- end
- else
- dir <= 0;
- end
- end
+ rapcore_harness harness0 (
+ .CLK(clock),
+ //.resetn_in(resetn),
+ .CHARGEPUMP(mprj_io[15]),
+ .analog_cmp1(mprj_io[25]),
+ .analog_out1(mprj_io[27]),
+ .analog_cmp2(mprj_io[26]),
+ .analog_out2(mprj_io[28]),
+ .PHASE_A1(mprj_io[23]),
+ .PHASE_A2(mprj_io[19]),
+ .PHASE_B1(mprj_io[16]),
+ .PHASE_B2(mprj_io[20]),
+ .PHASE_A1_H(mprj_io[21]),
+ .PHASE_A2_H(mprj_io[18]),
+ .PHASE_B1_H(mprj_io[14]),
+ .PHASE_B2_H(mprj_io[17]),
+ .ENC_B(mprj_io[12]),
+ .ENC_A(mprj_io[13]),
+ .BUFFER_DTR(mprj_io[37]),
+ .MOVE_DONE(mprj_io[24]),
+ .HALT(mprj_io[29]),
+ .SCK(mprj_io[35]),
+ .CS(mprj_io[34]),
+ .COPI(mprj_io[22]),
+ .CIPO(mprj_io[36]),
+ .STEPOUTPUT(mprj_io[30]),
+ .DIROUTPUT(mprj_io[31]),
+ .STEPINPUT(mprj_io[32]),
+ .DIRINPUT(mprj_io[33]),
+ .ENINPUT(mprj_io[11]),
+ .ENOUTPUT(mprj_io[10])
+ );
caravel uut (
.vddio (VDD3V3),
@@ -253,37 +207,5 @@
.io3() // not used
);
- pwm_duty duty1(
- .clk(clock),
- .resetn(resetn),
- .pwm(analog_out1),
- .duty(target_current1)
- );
- pwm_duty duty2(
- .clk(clock),
- .resetn(resetn),
- .pwm(analog_out2),
- .duty(target_current2)
- );
- hbridge_coil hbridge_coil1(
- .clk(clock),
- .resetn(resetn),
- .low_1(phase_a1_l),
- .high_1(phase_a1_h),
- .low_2(phase_a2_l),
- .high_2(phase_a2_h),
- .current(current1),
- .polarity_invert_config(1'b0)
- );
- hbridge_coil hbridge_coil2(
- .clk(clock),
- .resetn(resetn),
- .low_1(phase_b1_l),
- .high_1(phase_b1_h),
- .low_2(phase_b2_l),
- .high_2(phase_b2_h),
- .current(current2),
- .polarity_invert_config(1'b0)
- );
endmodule
`default_nettype wire
