Update wrapper, add obstructed version
- pins are now a bit wider and extend slightly outside the core area
- added an obstructed version of the wrapper to be used for routing to
gurantee that none of the resources within the user area is taken
while top-level-routing
- the core ring is completely outside the project area as marked by the
boundary in the various views (TODO: resolve FastRoute issue with
non-zero origins)
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
deleted file mode 100644
index 50e0bd1..0000000
--- a/openlane/user_project_wrapper/config.tcl
+++ /dev/null
@@ -1,30 +0,0 @@
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) user_project_wrapper
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
-
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
-
-set ::env(CLOCK_PERIOD) "10"
-
-set ::env(FP_PDN_CORE_RING) 1
-set ::env(PDN_CFG) $script_dir/pdn.tcl
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2920 3520"
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
-
-set ::env(VERILOG_FILES_BLACKBOX) "\
- $script_dir/../../verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
-
-set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
-
-set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
new file mode 120000
index 0000000..d4a8f25
--- /dev/null
+++ b/openlane/user_project_wrapper/config.tcl
@@ -0,0 +1 @@
+../user_project_wrapper_empty/config.tcl
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index dd5c0d1..a1b085c 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -14,6 +14,10 @@
manual_macro_placement f
+set ::env(PDN_CFG) $script_dir/pdn1.tcl
+gen_pdn
+
+set ::env(PDN_CFG) $script_dir/pdn2.tcl
gen_pdn
global_routing_or
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl
index 4fe8996..f6d953c 100644
--- a/openlane/user_project_wrapper/pdn.tcl
+++ b/openlane/user_project_wrapper/pdn.tcl
@@ -1,38 +1,43 @@
# Power nets
-set ::power_nets vccd1
-set ::ground_nets vssd1
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+set ::power_nets $::env(_VDD_NET_NAME)
+set ::ground_nets $::env(_GND_NET_NAME)
pdngen::specify_grid stdcell {
name grid
core_ring {
- met5 {width 2 spacing 2 core_offset 3}
- met4 {width 2 spacing 2 core_offset 3}
+ met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
+ met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
}
rails {
- met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
}
straps {
- met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+ met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
+ met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
}
- connect {{met1 met4} {met4 met5}}
+ connect {{met4 met5}}
}
pdngen::specify_grid macro {
- power_pins "VPWR"
- ground_pins "VGND"
- blockages "li1 met1 met2 met3 met4"
+ instance "obs_core_obs"
+ power_pins $::env(_VDD_NET_NAME)
+ ground_pins $::env(_GND_NET_NAME)
+ blockages "li1 met1 met2 met3 met4 met5"
straps {
}
- connect {{met4_PIN_ver met5}}
+ connect {}
}
-set ::halo 0
+pdngen::specify_grid macro {
+ power_pins $::env(_VDD_NET_NAME)
+ ground_pins $::env(_GND_NET_NAME)
+ blockages ""
+ straps {
+ }
+ connect {}
+}
-# Metal layer for rails on every row
-set ::rails_mlayer "met1" ;
+set ::halo 0
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
set ::rails_start_with "POWER" ;
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
deleted file mode 100644
index 70640e0..0000000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ /dev/null
@@ -1,136 +0,0 @@
-#BUS_SORT
-#NR
-io_in\[15\]
-io_out\[15\]
-io_oeb\[15\]
-vssa1
-io_in\[16\]
-io_out\[16\]
-io_oeb\[16\]
-io_in\[17\]
-io_out\[17\]
-io_oeb\[17\]
-io_in\[18\]
-io_out\[18\]
-io_oeb\[18\]
-io_in\[19\]
-io_out\[19\]
-io_oeb\[19\]
-io_in\[20\]
-io_out\[20\]
-io_oeb\[20\]
-io_in\[21\]
-io_out\[21\]
-io_oeb\[21\]
-io_in\[22\]
-io_out\[22\]
-io_oeb\[22\]
-io_in\[23\]
-io_out\[23\]
-io_oeb\[23\]
-
-#S
-wb_.*
-wbs_.*
-la_.*
-user_clock2
-
-#E
-io_in\[0\]
-io_out\[0\]
-io_oeb\[0\]
-io_in\[1\]
-io_out\[1\]
-io_oeb\[1\]
-io_in\[2\]
-io_out\[2\]
-io_oeb\[2\]
-io_in\[3\]
-io_out\[3\]
-io_oeb\[3\]
-io_in\[4\]
-io_out\[4\]
-io_oeb\[4\]
-io_in\[5\]
-io_out\[5\]
-io_oeb\[5\]
-io_in\[6\]
-io_out\[6\]
-io_oeb\[6\]
-vssa1
-vssd1
-vdda1
-io_in\[7\]
-io_out\[7\]
-io_oeb\[7\]
-io_in\[8\]
-io_out\[8\]
-io_oeb\[8\]
-io_in\[9\]
-io_out\[9\]
-io_oeb\[9\]
-io_in\[10\]
-io_out\[10\]
-io_oeb\[10\]
-io_in\[11\]
-io_out\[11\]
-io_oeb\[11\]
-io_in\[12\]
-io_out\[12\]
-io_oeb\[12\]
-vdda1
-io_in\[13\]
-io_out\[13\]
-io_oeb\[13\]
-vccd1
-io_in\[14\]
-io_out\[14\]
-io_oeb\[14\]
-
-#WR
-io_in\[24\]
-io_out\[24\]
-io_oeb\[24\]
-vccd2
-vssa2
-io_in\[25\]
-io_out\[25\]
-io_oeb\[25\]
-io_in\[26\]
-io_out\[26\]
-io_oeb\[26\]
-io_in\[27\]
-io_out\[27\]
-io_oeb\[27\]
-io_in\[28\]
-io_out\[28\]
-io_oeb\[28\]
-io_in\[29\]
-io_out\[29\]
-io_oeb\[29\]
-io_in\[30\]
-io_out\[30\]
-io_oeb\[30\]
-io_in\[31\]
-io_out\[31\]
-io_oeb\[31\]
-vdda2
-vssd2
-io_in\[32\]
-io_out\[32\]
-io_oeb\[32\]
-io_in\[33\]
-io_out\[33\]
-io_oeb\[33\]
-io_in\[34\]
-io_out\[34\]
-io_oeb\[34\]
-io_in\[35\]
-io_out\[35\]
-io_oeb\[35\]
-io_in\[36\]
-io_out\[36\]
-io_oeb\[36\]
-io_in\[37\]
-io_out\[37\]
-io_oeb\[37\]
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
new file mode 120000
index 0000000..0717c4b
--- /dev/null
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -0,0 +1 @@
+../user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
